528 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 16, NO. 5, MAY 1997 Behavior and Testability Preservation Under the Retiming Transformation Aiman El-Maleh, Member, IEEE, Thomas E. Marchok, Member, IEEE, Janusz Rajski, Associate Member, IEEE, and Wojciech Maly, Fellow, IEEE Abstract—Recently, it has been shown that retiming has a very strong impact on the run time required for sequential, structural automatic test pattern generators (ATPG’s), as well as the levels of fault coverage and fault efficiency attained. In this paper, we show that, for circuits with no hardware reset or a global reset state, retiming preserves testability with respect to a single stuck- at fault test set by adding a prefix sequence of a predetermined number of arbitrary input vectors. We show that this result holds for test sets derived based on structural and functional methods, and based on the conventional and multiple observation time testing strategies. Furthermore, we derive the conditions under which synchronizing sequences are preserved under retiming. We show that a structural synchronizing sequence for a circuit drives any of its corresponding retimed circuits to an equivalent state. In addition, we show that functional synchronizing sequences are preserved under retiming by adding a prefix sequence of a predetermined number of arbitrary input vectors. The impact of retiming on ATPG complexity and test-set preservation under retiming suggest a new approach for enhancing the performance of structural, sequential ATPG’s. Experimental results show that high fault coverages can be achieved on high-performance circuits optimized by retiming with much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits. I. INTRODUCTION D UE to the steadily increasing demand for high- performance integrated circuits, performance optimiza- tion must be considered as a key step during each stage of the synthesis process. Synthesis tools must be able to synthesize circuits that meet performance constraints while optimizing other design parameters like area, power, and testability. Several efforts have been made for optimizing the perfor- mance of sequential circuits. These efforts can be classified into three different approaches. The first approach considers the portions of combinational logic between registers bound- aries, and uses combinational delay optimization techniques Manuscript received January 6, 1995; revised July 2, 1996 and May 9, 1997. This work was supported in part by a Scholarship from the Quebec Fonds pour la Formation de Chercheurs et l’Aide ` a la Recherche, a Research Grant from the Natural Sciences and Engineering Research Council of Canada, the Semiconductor Research Corporation under Contract 95-DC-068, and Intel Corporation. This paper was recommended by Associate Editor K.-T. Cheng. A. El-Maleh and J. Rajski were with MACS Laboratory, McGill University, Montreal, P.Q., Canada. They are now with Mentor Graphics Corporation, Wilsonville, OR 97070 USA. T. E. Marchok was with the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213 USA. He is now with Intel Corporation, Mountain View, CA 94040 USA. W. Maly is with the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213 USA. Publisher Item Identifier S 0278-0070(97)06160-5. (e.g., [38]) to optimize these blocks. This approach is restric- tive as it does not allow the optimization process to utilize the interaction between gates separated by register boundaries. The second approach, called retiming [16], [17], does not change the combinational logic structure, and involves moving registers across portions of combinational logic in order to reduce the clock cycle time. This approach will fail to satisfy timing constraints if, for example, there is a combinational critical path from a primary input to a primary output. In this case, combinational delay optimization techniques are essential. The third approach naturally combines the power of the first two approaches by using both retiming and com- binational delay optimization techniques. In [26], multilevel logic synthesis transformations were extended using retiming to be applicable across register boundaries by considering time-labeled variables. This technique was able to achieve a significant reduction in the cycle time of pipelined circuits and circuits synthesized from high-level description. Another technique for optimizing sequential circuits was proposed in [19] and [20] by using an extension of retiming, called pe- ripheral retiming, and combinational optimization techniques. This method has been shown to be effective in increasing the performance of pipelined circuits. In order to improve the effectiveness of retiming, a technique was proposed in [6] that identifies and eliminates the bottlenecks in a sequential circuit which prevent retiming to achieve a desired clock period. This technique has shown a significant improvement of performance as compared to retiming the original cir- cuit. Retiming and resynthesis have also been shown in [4] to improve the performance of circuits beyond what is achievable using optimal retiming and combinational delay optimization techniques. Due to the effectiveness of retiming, new implementations have been recently explored in [37] to handle industrial designs. It has also been extended for sequential circuits with transparent latches [36] and with multiphase clocking schemes [2]. In addition, it has been used with algebraic transformations for critical path reduction in high-level synthesis [14]. While retiming is traditionally used for optimizing area and performance, it has also been recently used to enhance testability. In [15], retiming is used to reduce the number of registers required for partial scan to break the cyclic structure of the sequential circuit. It was proposed that minimizing the number of registers by retiming is a good heuristic for minimizing the number of registers required for partial scan. The work in [7] uses retiming to enhance circuit testability 0278–0070/97$10.00  1997 IEEE