Utilizing Synthesis to Verify Boolean Function Models Azam Beg, Prasad P.W.C., Walid Ibrahim College of Information Technology UAE University, Al-Ain United Arab Emirates {abeg, prasadc, walidibr}@uaeu.ac.ae Emad Abu Shama Tundra Semiconductor Corporation 603 March Road Kanata, Ontario, Canada emad.abu-shama@tundra.com Abstract — In this paper, we compare two different Boolean function reduction methods in order to justify the analytical model of the Monte Carlo data for Boolean function complexity. We use a Binary Decision Diagram (BDD) complexity model (proposed earlier) and weigh it against the complexity behavior generated by Synopsys Design Compiler (DC). We use this synthesis tool (that utilizes a standard cell library) to generate RTL hardware description of Monte Carlo circuits as gate-level netlists. The two reduction methods (model and DC) transform an arbitrary function into a much- reduced representation of the same function. The comparison confirms that the behavior of Boolean function complexity using the model and the DC is visually and statistically similar; the similarity holds true for BDDs representing functions comprising a wide range of variables and minterms. I. INTRODUCTION Logic level simulation is still one of the most often used operations in digital systems during both design and test stages [1], [2]. The complexity of digital integrated circuits (ICs) has been increasing exponentially since a long time, at least since Shannon's [3] pioneering paper, with the number of components or devices in a single IC more than doubling every 18 months. Some current ICs contain over billion of devices, and a similar number of wires connecting them in a very small chip area. In particular, Boolean function representation has a direct influence on the computation time and space requirements of digital circuits and most of the problems in VLSI/CAD designs can be formulated in terms of Boolean functions. Research on the complexity of Boolean functions in non-uniform computation models is now part of one of the most interesting and important areas in theoretical computer science [1], [4]. Mathematicians and computer scientists keep trying to classify Boolean functions according to various complexity measures, such as the minimal size of circuits needed to compute specific functions [5], [6], [7]. The time required for computation of a particular function can be reduced in two different ways, either using better computers or better algorithms. All algorithms for the minimization of Boolean functions begin with the computation of prime implicants. Many tasks in the design and verification of digital systems involve large propositional formulae. It is therefore important to have efficient ways of representing and manipulating such formulae. In recent times, BDDs have emerged as the representation of choice for many applications. BDDs were originally proposed as a data structure for efficient Boolean function representation and manipulation by Lee and Akers [8], and were further developed by Bryant [9]. Due to their compactness, the BDDS have also been frequently used in logic synthesis approaches. Furthermore, by using BDDs, many operations can be carried out efficiently, such as estimating area and power, or considering layout aspects. In many applications, the efficiency of BDD representations is determined by the size of the BDD which in turn is defined as the number of nodes (size) in the BDD for a given Boolean function. The variable ordering has a direct impact on the size of the BDD, and determining an optimal variable ordering is an NP-hard problem [9]. Evaluation of space complexity of Boolean functions can be performed by determining the area (size) of the BDD. Building the complete BDD can increase the time complexity of the design process, because more time may be needed to implement, verify and test the design. Modeling is considered to be a time-efficient alternative to actual simulations and prototyping, especially for non-linear and multi-variable systems. Predicting complexity of a Boolean function that represents a digital circuit could be a good indication of its feasibility prior to engaging in any further development and implementation. There has been a lot of research [4], [5], [10] on the estimation of combinational and sequential circuit parameters from the exact Boolean functions describing the circuit. The authors (and co-authors) of this paper presented mathematical and neural network models to predict the complexity of Boolean functions and XOR/XNOR minterms, and the path length of BDDs [5], [6], [7].