Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach Sudhanva Gurumurthi Anand Sivasubramaniam Mary Jane Irwin N. Vijaykrishnan Mahmut Kandemir Dept. of Computer Science and Engineering The Pennsylvania State University, University Park, PA 16802 gurumurt,anand,mji,vijay,kandemir @cse.psu.edu Tao Li Lizy Kurian John Dept. of Electrical and Computer Engineering University of Texas at Austin, Austin, TX 78712 tli3,ljohn @ece.utexas.edu Abstract Power dissipation has become one of the most critical factors for the continued development of both high-end and low-end computer systems. The successful design and eval- uation of power optimization techniques to address this vi- tal issue is invariably tied to the availability of a broad and accurate set of simulation tools. Existing power simula- tors are mainly targeted for particular hardware compo- nents such as CPU or memory systems and do not capture the interaction between different system components. In this work, we present a complete system power simulator, called SoftWatt, that models the CPU, memory hierarchy and a low-power disk subsystem and quantifies the power behavior of both the application and operating system. This tool, built on top of the SimOS infrastructure, uses validated analytical energy models to identify the power hotspots in the system components, capture relative contributions of the user and kernel code to the system power profile, identify the power-hungry operating system services and charac- terize the variance in kernel power profile with respect to workload. Our results using Spec JVM98 benchmark suite emphasize the importance of complete system simulation to understand the power impact of architecture and operating system on application execution. 1 Introduction Performance optimization has long been the goal of dif- ferent architectural and systems software studies, driving technological innovations to the limits for getting the most out of every cycle. This quest for performance has made it possible to incorporate millions of transistors on a very small die, and to clock these transistors at very high speeds. While these innovations and trends have helped provide tremendous performance improvements over the years, they have at the same time created new problems that demand immediate consideration. An important and daunting prob- lem is the power consumption of hardware components, and the resulting thermal and reliability concerns that it raises. As power dissipation increases, the cost of power delivery to the increasing number of transistors and thermal packaging for cooling the components goes up significantly [3, 33]. Cooling systems need to be designed to tackle the peak power consumption of any component. These factors are making power as important a criterion for optimization as performance in commercial high end systems design. Just as with performance, power optimization requires careful design at several levels of the system architecture [13]. At the circuit level, several techniques such as clock gating, supply voltage scaling and supply voltage gating have been proposed to reduce both dynamic and leakage power [5]. Architectural level power saving techniques typ- ically detect idleness of components not being used and appropriately transition them to a lower power consuming mode. Even the software - the operating system (OS), com- piler and the application - has an important role to play in power efficient systems design. The operating system, which plays the role of hardware manager, can schedule jobs [23], allocate and manage memory [19], and control peripherals [20] to reduce overall system power. The com- piler can generate code and data transformations to increase idleness of hardware components so that they can be tran- sitioned to low power modes more effectively [7] Finally, algorithmic transformations in the application have been shown to give significant power savings [30]. The successful design and evaluation of such optimiza- tion techniques is invariably tied to a broad and accurate set of rich tools that are available for conducting these stud- ies. The crucial role of design and evaluation tools for per- formance optimization has been well illustrated by several studies over the years, and the community at large is cur- rently expending a lot of effort in the development of sim- ilar tools for power estimation and optimization. There are tools to facilitate this at the circuit [1], gate [32], and ar- Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA02) 1503-0897/02 $17.00 ' 2002 IEEE