712 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 4, APRIL 1999 An 0.3- m Si Epitaxial Base BiCMOS Technology with 37-GHz and 10-V BV for RF Telecommunication Hideaki Nii, Chihiro Yoshino, Sadayuki Yoshitomi, Kazumi Inoh, Hiromi Furuya, Hiroomi Nakajima, Hiroyuki Sugaya, Hiroshi Naruse, Yasuhiro Katsumata, Member, IEEE, and Hiroshi Iwai, Fellow, IEEE Abstract— In this paper, an 0.3- m BiCMOS technology for mixed analog/digital application is presented. A typical emitter area of this technology is m m. This technology includes high of 37 GHz at the low collector current of 300 A and high BV of 10 V NPN transistor, CMOS with m, and passive elements. By using the shallow and deep trench isolation technology and nonselective epitaxial intrinsic base, the can be reduced to 1.6 fF, which is the lowest value reported so far. As a results, we have managed to obtain the high at the low current region and high BV concurrently. These features will contribute to the development of high- performance BiCMOS LSI’s for various mixed analog/digital applications. Index Terms— Base, BiCMOS, bipolar, epitaxy, high-fre- quency. I. INTRODUCTION R ECENTLY, the market for analog RF LSI’s for mo- bile communication systems, such as PHS or cellular, has been growing rapidly. BiCMOS technology with high- performance and low-power consumption NPN and CMOS has shown great potential for combining analog and digital com- ponents for use in such applications [1]–[15]. The success of this technology will make it possible for mixed analog/digital signal for various applications to be processed on a single BiCMOS chip. However, the integration of high-performance NPN with CMOS involves several problems. One of these is the problem of poor BV [3], [6]. Table I shows the summaries of previously reported high-performance NPN transistors only in the BiCMOS regime. The table indicates that high-performance NPN transistors, which had SiGe base or low-energy ion implanted base, gen- erally showed superior high-frequency characteristics, but low BV [1], [6], [8], [10], [12]. An outline of the technologies used in those transistors is presented below. In 1994, Chih Hsin Wang et al. presented a single-poly BiCMOS technology which featured high of 30 GHz for Mnauscript recevied October 8, 1997; revised August 20, 1998. The review of this paper was arranged by Editor T. Nakamura. H. Nii, C. Yoshino, S. Yoshitomi, K. Inoh, H. Furuya, H. Nakajima, Y. Katsumata, and H. Iwai are with Microelectronics Engineering Laboratory, Toshiba Corporation, Kawasaki 210-8582, Japan. H. Sugaya and H. Naruse are with the Semiconductor Group, Toshiba Corporation, Kawasaki 210-8582, Japan. Publisher Item Identifier S 0018-9383(99)02388-6. low-power mixed analog/digital applications. This single-poly bipolar process had a superior compatibility with CMOS-based process and it was easily integrated as BiCMOS with only additional two masks. But, its BV of 4.0 V was relatively low [12]. In the same year, Y. Kinoshita et al. showed 0.25- m BiCMOS technology for ECL BiCMOS which achieved a delay time of sub-30-ps. It used heavily boron-doped epitaxial contact (HYDEC) technology which solved several problems which arise in BiCMOS integration. The of NPN transistor reached 22.6 GHz, but BV was 4.1 V [10]. In 1994, 1995, and 1996, Harame et al. presented the BiCMOS technology which uses epitaxial SiGe base for wireless telecommunication system [1], [6], [8]. IBM adopted the shallow and deep trench isolation to lower the parasitic capacitance and showed superior high-frequency character- istics, notably peak and reach to 35–50 GHz and 50–60 GHz, respectively, with BV of 3.3–3.45 V. This low BV becomes an important problem when BiCMOS LSI’s are produced. Even if the supply voltage is lowered below BV , the problem does not disappear, because, the problem of low BV is caused by the burn-in screening procedure which is desirable for BiCMOS LSI’s before they are forwarded. The procedure is required to ensure the reliability of the gate dielectric oxide of the CMOS. The voltage during burn-in screening is 5.0 V–5.5 V in m generation, and in 0.25- m–0.30- m generation it will be reduced to 4.0–4.5 V. In the BiCMOS production regime, BV has to exceed this burn-in screening voltage. We have therefore developed an NPN bipolar transistor, which has high BV that exceeds the burn-in screening voltage as well as excellent high-frequency characteristics. This was done by greatly reducing the parasitic capacitance, adopting a flat impurity profiled base that is epitaxially grown, and optimizing the collector epitaxial layer thickness [16]. In this paper, we present this new highly integrated 0.3- m BiCMOS technology which achieves of 37 GHz while maintaining BV of 10 V. These characteristics give BiC- MOS LSI’s the potential to be useful in various mixed analog/digital systems. The structure and the fabrication process are explained in the next section, and the measurement results and discussions are presented in the following section. In the final section, the summary and conclusions are given. 0018–9383/99$10.00  1999 IEEE