2264 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. zyxwv 40, NO. 12, DECEMBER zyxw 1993 P-MOSFET’s with Ultra-Shallow Solid-Phase- Diffused Drain Structure Produced by Diffusion from BSG Gate-Sidewall Masanobu Saito, Takashi Yoshitomi, Hisashi Hara, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Hisayo Sasaki Momose, Yasuhiro Katsumata, Yukihiro Ushiku, and Hiroshi Iwai, zyxwvuts Senior Member, zyxwvu IEEE Abstract-A p-MOSFET structure with solid-phase-diffused drain (SPDD) is proposed for future 0.1 pm and sub-0.1 pm devices. Highly doped ultra-shallow p+ source and drain junc- tions have been accomplished by solid-phase diffusion from the highly doped BSG sidewall. The resulting shallow, high-con- centration drain profile significantly improves short channel ef- fects without increasing parasitic resistance. At the same time, an zyxwvutsrqpo in situ highly boron-doped LPCVD poly-silicon gate is intro- duced to prevent the transconductance degradation which arises in ultra-small p-MOSFET’s with lower process temperature as a result of depletion formation in the p+-poly-silicon gate. It is confirmed that excellent electrical characteristics and good hot- carrier reliability are achieved, thus making the structure suit- able for future 0.1 pm and sub-0.1 pm devices. I. INTRODUCTION XTENSIVE studies of 0.1 pm MOSFET’s have been E carried out zyxwvutsrqp [ 11-[8] to test their potential for applica- tion in future ULSI’s, since these are the most advanced devices which can be experimentally produced with cur- rent technology. As device dimensions of devices falls to 0.1 zyxwvutsrq pn and below, ultra-shallow source and drain junc- tions will become essential to prevent short-channel ef- fects. At the same time, the dopant concentration in the source and drain regions should be sufficiently high to re- duce parasitic resistance in these regions. Such shallow source and drain regions with sufficiently high dopant concentrations can be realized in the case of n-MOSFET’s by adopting an LDD structure produced by ion implantation; there have been several reports on 0.1 zyxwvu pm devices of this type [1]-[7]. In the case of p-MOS- FET’s, on the other hand, it is relatively difficult to fab- ricate extremely shallow junctions of adequate concentra- tion by implanting B or BF2 because of boron’s relatively high diffusibility and the tailing effects of ion implanta- tion [9]; the result is that only a few reports have appeared on 0.1 pm p-MOSFET’s [2], [3], [7], [8]. In implement- ing ion implantation of B or BF2, the pre-amorphizing Manuscript received December 17, 1992; revised June 21, 1993. The review of this paper was arranged by Associate Editor J. R. Pfiester. The authors are with Research and Development Center, Toshiba Cor- poration, Kawasaki 210, Japan. IEEE Log Number 9212634. technique will be an effective way to prevent channeling effects [8]. It is known that solid-phase diffusion from the highly doped BSG yields very steep boron profiles [lo], [ 113. By making use of the BSG sidewall and rapid thermal an- nealing (RTA), extremely shallow junctions with high concentration-suitable for 0.1 ,um p-MOSFET’s-can be achieved. In the development of ultra-small p-MOSFET’s, cer- tain other considerations are also important. Firstly, it is usual to use the p+-poly-silicon gate instead of the con- ventional nf-poly-silicon gate to suppress short-channel effects [ 121. The formation of a depletion layer in the p+- poly-silicon gate is another problem of conventional bo- ron-implanted poly-silicon gate MOSFET’s [13], [ 141 as lower process temperatures are used to suit reduced de- vice dimensions. With low process temperatures, im- planted boron atoms in the poly-silicon gate sometimes fail to activate sufficiently and sometimes the boron depth profile in the poly-silicon gate is nonuniform, resulting in a low concentration of activated boron in the poly-silicon gate near the gate oxide. This results in the formation of a depletion layer. Such a depletion layer in the poly-sili- con gate reduces the transconductance of the p-MOSFET [ 151. In situ highly boron-doped LPCVD poly-silicon [ 161 gates suppress depletion layer formation. Boron penetra- tion from the p+-poly-silicon gate into the silicon sub- strate is a further problem for 0.1 pm p-MOSFET’s with ultra-thin gate insulator films. A nitrided-oxide gate in- sulator prevents the subthreshold slope degradation caused by boron doping of the substrate [17], [18]. In this paper, we propose a new SPDD structure based on in-situ boron-doped LPCVD poly-silicon gates and ni- trided-oxide gate insulator films suitable for future 0. l pm and sub-0.1 pm p-MOSFET’s. Excellent electrical char- acteristics and good hot-carrier reliability are confirmed. 11. EXPERIMENTAL RESULTS A. The SPDD Structure and Sample Fabrication zyx 1) m e SPDD Structure: Fig. l(a) is a schematic cross section of the new SPDD p-MOSFET. A conventional 0018-9383193$03.00 zyxwvut 0 1993 IEEE