1858 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 8, AUGUST 2006 Charge Trapping in High-k Gate Stacks Due to the Bilayer Structure Itself John R. Jameson, Peter B. Griffin, James D. Plummer, Fellow,IEEE, and Y. Nishi, Fellow,IEEE Abstract—Charge trapping at the interface between the two dielectric layers of a high-k gate stack is shown to be caused by Maxwell–Wagner instability, which is the following. The fact that the high-k and interfacial layers have different compositions means that they will also have different conductivities. Then, a gate bias will produce a discontinuity in current at their interface, causing charge to accumulate there until, in steady state, the same current flows through both layers. Maxwell–Wagner instability is shown to be coupled to a second instability, dielectric relaxation of the high-k layer; continuity of current in steady state requires that the electric fields in the two dielectric layers remain fixed, so the change in polarization of the high-k layer due to dielectric relaxation must be compensated for by the conduction of addi- tional charge to the interface. Evidence for this behavior in high-k gate stacks is found in the thickness dependence of their dielectric relaxation current, with the correct dependence being obtained only from a model in which the two instabilities act simultaneously. Uniform dielectrics do not exhibit Maxwell–Wagner instability, and perfect crystals do not exhibit dielectric relaxation, making the ideal high-k gate dielectric a uniform single-layer perfect crystal bonded epitaxially to the Si substrate. Index Terms—Amorphous materials, bilayer dielectrics, charge trapping, dielectric relaxation, high-k dielectrics, Maxwell– Wagner polarization, threshold voltage instability, transition- metal oxides. I. INTRODUCTION T RANSITION-METAL oxides have been leading candi- dates in the quest to replace the traditional SiO 2 gate dielectric of MOS transistors with a material having a higher dielectric constant. Unfortunately, all of the transition-metal oxides considered to date seem to share two deficiencies. First, they all cause an SiO 2 -like interfacial layer to grow when they are deposited directly on Si [1]. Second, they all produce electrical instabilities in MOS devices. Electrical instabilities have been the subject of numerous experimental studies [2]–[8], and it seems possible to interpret many of them as arising from the trapping of charge somewhere within the gate stack. In particular, the high-speed experiments of Kerber et al. [2], [3] seem to paint a vivid picture of electrons filling up a gate stack when a gate bias is applied, then rushing out after the bias is removed, producing dramatic instabilities in the drain current of transistors at short timescales. By cycling the gate Manuscript received June 22, 2005; revised January 30, 2006. This work was supported by the Initiative for Nanoscale Materials and Processes. The work performed at the Stanford Nanofabrication Facility of NNIN was supported by the National Science Foundation under Grant ECS-9731293. The review of this paper was arranged by Editor M.-C. Chang. The authors are with the Center For Integrated Systems, Stanford University, Stanford, CA 94305-4075 USA (e-mail: jameson@stanford.edu). Digital Object Identifier 10.1109/TED.2006.877700 voltage on and off [2]–[5], one also observes gradual shifts in the properties of devices, implying that the electrons that flow into the gate stack while the bias is on do not have time to flow out completely when the bias is off. For high-k gate stacks to be suitable for commercial devices, these electrical instabilities must be eliminated, so it is im- perative to understand why charge trapping takes place. It has been widely accepted that the trapped charge resides in local- ized electronic states associated with structural defects [2]–[8]. However, “What is the electronic structure of the trapped charge?” is not the same question as “Why does the charge accumulate there in the first place?” The purpose of this paper is to suggest that the bilayer structure itself causes charge to accu- mulate in high-k gate stacks, for the following reason. The fact that the two layers of a high-k gate stack have different compo- sitions means that they will also have different conductivities 1 . Then, the application of a gate bias will immediately produce a discontinuity in current density at the interface between the two layers, causing charge to accumulate there until, in steady state, the same current density flows through both layers. If the gate bias is removed, a discontinuity in current density will again be produced, this time causing the charge to rush out of the gate stack, as the experiments described above seem to suggest. To the authors’ knowledge, this behavior has not previously been discussed in the literature on high-k gate stacks. How- ever, it is a well-known and ancient phenomenon, having first been described in the 19th century by Maxwell himself [11], then somewhat later and more extensively by Wagner [12]. Nowadays, it is called “Maxwell–Wagner polarization,” though in the present paper, we will refer to it as “Maxwell–Wagner instability” to emphasize its time-dependent nature. The reader is referred to the text by von Hippel [13] for a discussion of aspects of the phenomenon not considered here, such as its effect on the frequency response of a bilayer capacitor. Maxwell–Wagner instability occurs in every composite dielec- tric system, and semiconductor devices have provided several well-known examples besides high-k gate stacks. The most famous of these is the traditional MOS structure, whose ac- cumulation (or inversion) layer develops precisely because the conductivity of the SiO 2 layer is much too low to conduct away the charge carried to the interface by the Si. Indeed, “accumulation layer” would also seem an appropriate term for the charge that builds up at the interface between the two layers 1 We use the term “conductivity” to refer to the general field-current char- acteristic of a layer, which could have contributions from a variety of sources (e.g., tunneling, emission over a Schottky barrier, etc.), but which is generally not a simple linear relation between the field and current (as in a metal). 0018-9383/$20.00 © 2006 IEEE