JOURNAL OF ELECTRONIC TESTING: Theory and Applications, 4, 345-360 (1993) 9 1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. Fault Simulation of Linear Analog Circuits NAVEENA NAGI Computer Engineering Research Center, University of Texas at Austin, Austin, TX 78758 ABHIJIT CHATTERJEE School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA 30332 JACOB A. ABRAHAM Computer Engineering Research Center, University of Texas at Austin, Austin, TX 78758 Received March 10, 1993; Revised May 10, 1993. NAGI@CERC.UTEXAS.EDU Editor: M. Soma Abstract. Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to the discrete Z- domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation. 1. Introduction Analog circuits and systems have recently enjoyed a renaissance, due to advances in communications and high-speed VLSI ASICs which demand a tightly coupled analog-digital architecture. However, the state of the art in analog automatic test generation is not as advanced as in digital automatic test pattern generation. Most previous work in test generation focuses on digital circuits using the classical stuck-at fault model since most potential physical faults can be mapped to a node stuck-at a logical 1 or 0. However, because of the com- plex electrical nature of analog circuits, a direct appli- cation of digital fault models proves to be inadequate in capturing the faulty behavior. Hence, analog test selection has been approached in a rather ad hoc way. Sometimes circuits tend to be overtested, while at other times, the tests may be inadequate. Traditionally, fault simulation is used to determine the effectiveness of input test sets to distinguish good chips from defective ones for digital circuits. However, for today's complex analog circuits with thousands of faults, fault simulation using conventional circuit simulators will be very inefficient. The problem is com- pounded by the presence of transient (ac) errors which can be detected only by an input waveform over time, unlike dc errors which require a single set of steady- state inputs. While the problem of fault simulation for analog cir- cuits has not been directly addressed by previous re- searchers, there has been related work in other areas. FSPICE [1] is a SPICE based tool to introduce faults at the circuit level and simulate these faulty circuits using SPICE. Since fault simulation of large circuits at the circuit level is too time consuming to be prac- tical, FSPICE is used for the simulation of macrocells and the results of the simulation used for the develop- ment of logical and functional fault models. Over the past few years, a number of higher level simulation tools for analog circuits have been developed including SABER [2] and iMACSIM [3], to name a few. These have alleviated the problem of large simulation times of circuit simulators. However, none of these have been applied to the problem of fault simulation and fault modeling. The lack of suitable analog fault models has been the prime reason for restricting the problem of analog test to the functional domain. Numerous authors have addressed the analog and mixed signal testing problem but all these techniques focus on functional testing of specific classes of circuits, for example, codecs [4], and do not indicate test generation methodologies nor the efficiency of the tests. Recent research [5, 6] has at- tempted to move away to the more quantitative fault- based approach to analog testing. However, the fault models are limited to resistive faults [5], or faults