978-1-4673-0236-4/12/$31.00 © 2012 IEEE PROC. 28th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2012), NIŠ, SERBIA, 13-16 MAY, 2012 Clock Jitter Generator with Picoseconds Resolution G. Jovanoviü, M. Stojþev, T. Nikoliü and Z. Stamenkoviü Abstract - As CMOS technology has scaled, supply voltage has dropped, chip power consumption has increased, and clock frequency has increased, the effects of jitter become critical and jitter budget gets tighter. Jitter can be decomposed into several components, each having specific sets of characteristics and root causes. This paper presents a short review of jitter fundamentals including a discussion of the various random and deterministic jitter components, and a method for jitter analysis and injection in computer clock signal. This method gives test engineers a deeper insight into interaction of the jitter components. The overall hardware structure of a jitter generator, which uses digital and analog techniques, based on a voltage controlled delay line is described too. I. INTRODUCTION Clock jitter is probably one of the most obscure phenomena in synchronous digital circuits [1]. It basically describes the timing errors in the clocking operation due to clock disturbances. To measure jitter in the time domain, the timing signal is typically compared to a “perfect reference signal”. The variations of the timing signal’s rising and falling edges as compared to the perfect reference are defined as jitter, and the corresponding time- variation measurements are specified in time units as small as picoseconds. In order to evaluate system performance in respect to jitter tolerance, a jitter generator is indispensable. The jitter generator should generate and inject different kinds of jitter into the input data stream in a controllable fashion [2], [3]. In this paper, we propose a programmable jitter generator, which targets all the aforementioned challenges. We investigate how the jitter components can be modeled and combined, and how the total jitter can be adjusted injecting small portions of different jitter components. II. BACKGROUND ABOUT JITTER Jitter can be categorized in many different ways [4]. We use a categorization based on the jitter phenomenological properties. The first classification is between a jitter that is random and the other that is not. The jitter that is not random is bounded, i.e. its magnitude is finite. In contrast, the random jitter is unbounded and, within physical limits, can theoretically reach any magnitude. The second classification is between a jitter which is correlated to the data sequence or pattern and the other that occurs independently of the data. These can be referred to as correlated and uncorrelated jitters. The total jitter (J T ) results from a combination of the random jitter (J R ) and the deterministic jitter (J D ). Each jitter component has some specific corresponding root causes and characteristics. III. PROGRAMMABLE CLOCK JITTER GENERATOR The structure of a programmable jitter generator (PJG) is presented in Figure 1. Main building blocks of PJG are: Phase Locked Loop (PLL) circuit – it accepts at its input a referent signal with frequency f CLK and generates an output signal with frequency f 0 =N ·f CLK , N  1. In respect to the hardware structures of its building blocks, phase detector (PD PLL ), charge pump (CP PLL ), low-pass filter (LPF PLL ), voltage controlled oscillator (VCO PLL ), and divider (/N), the phase locked loop circuit represents one classical design solution [5]. Specific to the PLL circuit is a Delay Locked Loop (DLL) as constituent of the feedback path. In the proposed design, a Voltage Controlled Delay Line (VCDL) composed of n voltage controlled delay cells of identical structure and delay time is used to generate n signals with different coarse-grain phase shifts. Signal Selector (MUX n:1 ) – it is a digital multiplexer with one output pin S M and n input pins named as U 0 , U 1 ,.., U n–1 , respectively. Signal selection lines S 0 , S 1 …S k-1 select the output of a corresponding delay buffer cell and connect it to the output pin S M . MUX n:1 provides coarse-grain phase shift selection. Linear voltage controlled Delay Element (LDE) – it is intended for fine grain phase shifting [6]. The amount of a phase shift is defined by the output signal of a digital-to- analog converter (DAC). Address Generator (AG) – it is composed of two entities. Each consists of a pseudo Random Generator (RG CG /RG FG ) and a histogram memory (HM CG /HM FG ). The indices CG and FG relate to the coarse-grain and fine-grain entities, respectively. The RG CG /RG FG is used for the generation of random addresses intended for accessing the histogram memory. As result of combining several jitter components, different jitter sequences can be generated. Histogram values that are calculated using Matlab are stored in memory which, in this case, acts as a look-up table. At the beginning of jitter generation process, the MCU loads the HM CG /HM FG with values that correspond to the probability density function (PDF) of different deterministic and G. Jovanoviü, M. Stojþev, and T. Nikoliü are with the Department of Electronics, Faculty of Electronic Engineering, University of Niš, Aleksandra Medvedeva 14, 18000 Niš, Serbia, E-mail: goran.jovanovic{mile.stojcev,tatjana.nikolic}@elfak.ni.ac.rs Z. Stamenkoviü is with the IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany, E-mail: stamenkovic@ihp- microelectronics.com