654 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 3, MARCH 2010 Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS Ramesh Vaddi, S. Dasgupta, and R. P. Agarwal, Senior Member, IEEE Abstract—Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium per- formance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy con- sumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and en- vironmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS. From the study, we conclude that alternative devices like double- gate silicon-on-insulator (DGSOI) are better candidates in terms of performance, robustness and PVT insensitivity as compared to bulk circuits for both static CMOS and pseudo NMOS logic families. We also study the performance and robustness compar- isons of bulk CMOS and DGSOI subthreshold basic logic gates with and without parameter variations and we observe 60–70% improvement in power delay product and roughly 50% better tolerance to PVT variations of DGSOI subthreshold logic circuits compared to bulk CMOS subthreshold circuits at the 32 nm node. Index Terms—Device/circuit co-design, double-gate silicon- on-insulator (DGSOI), HSPICE, process, voltage, and tempera- ture (PVT) variations, robust, subthreshold logic, ultralow power. I. I NTRODUCTION I N MOST of the earlier very large-scale integration (VLSI) applications, clock speed and silicon area used to be the dominating metrics of performance. However, in recent years, for all modern VLSI applications, the demand for energy constrained design has increased tremendously due to several factors, like increased problems of leakage currents, thermal management, heat removal, and reliability. Along with these problems, there is also an increasing class of applications, like portable electronics, microsensors, radio frequency identi- fication, laptops, cell phones, and cameras, that demand very low power consumption and prolonged battery life. All of Manuscript received September 11, 2009. First published February 2, 2010; current version published February 24, 2010. The review of this paper was arranged by Editor D. Esseni. R. Vaddi and S. Dasgupta are with the Semiconductor Devices and Very Large-Scale Integration Technology Group, Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee 247 667, India (e-mail: sudebfec@iitr.ernet.in). R. P. Agarwal is with Shobhit University, Meerut 250 110, India. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2009.2039529 these applications motivated the designers to come up with several power reduction methods such as supply voltage scal- ing, switching activity reduction, architectural techniques of pipelining, device sizing, and interconnect. Out of all these methods, one that is successful is supply voltage scaling, which significantly reduces both active and static components of power. An extreme case in supply voltage scaling is subthresh- old circuit design, where the devices enter the subthreshold region of operation (supply voltage less than the threshold voltage of devices). It has been proved that by operating in the subthreshold region, circuits consume minimum energy per operation [1]–[4]. The key advantages of operating devices in the subthreshold region compared to superthreshold region (V dd >V th ) are reduced power due to low V dd and small gate capacitance [5]. Moreover, due to exponential I –V characteristics in the sub- threshold region, the devices will have a high transconductance gain [6] and, thus, near-ideal voltage transfer characteristics (VTCs) and better noise margins as a fraction of V dd (= NM L /V dd ), although absolute values may reduce [5]. The drawbacks of operating in the subthreshold region are reduced speed and increased sensitivity to process, voltage, and temper- ature (PVT) variations (due to exponential I –V characteristics). It has been shown recently that devices can also be optimized for subthreshold operation to improve performance with further reduction in power consumption [7]–[9]. Very few researchers have analyzed and examined the sen- sitivity variation of subthreshold devices and circuits and have proposed various techniques to manage and mitigate variability in subthreshold circuits to increase their robustness [10]–[14], such as proper circuit sizing and choice of circuit logic depth [10], [13], upsizing [11], yield optimization [12], and body bias [14]. Consideration of double-gate silicon-on-insulator (DGSOI) devices for optimal subthreshold operation has also been presented recently [15]–[18]. These devices have been given considerable attention for analyzing superthreshold cir- cuit behavior with progressive technology scaling, though no such attention has been given as to how subthreshold circuits behave for progressive technology scaling using DGSOI de- vices. To the best of our knowledge, no paper emphasizes the variation of all key device and environmental parameters on subthreshold circuit performance for advanced technology nodes such as 32 nm. In this paper, we have combined two important issues for subthreshold operation, i.e., PVT varia- tion sensitivity along with a detailed analysis of subthreshold 0018-9383/$26.00 © 2010 IEEE