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Copyright Statement: ISSN 0282-1724/02/$17.00 2002 IEEE.
Manuscript received 27 June 2001; accepted 3 September 2001. This
paper is published herein in its entirety.
A New Algorithm for the Generation of
Reference Voltages of a DVR Using the Method
of Instantaneous Symmetrical Components
Arindam Ghosh, Avinash Joshi
Author Affiliation: Department of Electrical Engineering, Indian
Institute of Technology, Kanpur, India.
Abstract: This letter presents a new method for the generation of
reference voltage for a dynamic voltage restorer (DVR). These volt-
ages, when injected in series with a distribution feeder by a voltage
source inverter, can tightly regulate the voltage at the load terminal
against imbalance or harmonics in the source side. It is stipulated that
the DVR does not supply any real power in the steady state. The refer-
ence voltage generation scheme is validated through digital computer
simulation studies.
Keywords: Dynamic voltage restorer, series compensation.
Introduction: A power electronic converter-based series compen-
sator that can protect critical loads from supply side voltage distur-
bances other than outages is called a dynamic voltage restorer (DVR). It
injects a set of three-phase ac output voltages in series with the distribu-
tion feeder voltages. The amplitude and phase angle of the injected
voltages are variable, thereby allowing control of the real and reactive
power exchange between the DVR and the distribution system. This
letter extends the concept of dynamic voltage restoration further to dis-
cuss a DVR that can tightly regulate the load voltage without any real
power consumption in the steady state. It can also perform the primary
functions of the restorer—i.e., to protect the load from temporary volt-
age interruption, sag/swell, etc. In particular, the reference voltage gen-
eration scheme for the DVR is discussed. These voltages, when
injected in series with the system via an inverter, perform the desired
task of voltage regulation. The voltage generation scheme is validated
through extensive simulation studies.
Expression for Real Power in Terms of Instantaneous Symmet-
rical Components: In this section we define the real power in terms of
instantaneous symmetrical components. These components are defined
for three instantaneous currents i
a
, i
b
, and i
c
as [1]
i
i
i
i
a a
a a
i
a
a
a
a
012
0
1
2
2
2
1
3
1 1 1
1
1
=
=
a
b
c
i
i
(1)
where a e
j
=
° 120
and zero, positive, and negative sequence currents are
denoted by subscripts 0, 1, and 2, respectively. It is to be noted that i
a 0
is
zero for balanced currents and the phasor i
a 2
is the complex conjugate of
the phasor i
a 1
. A similar transformation can also be defined for voltages.
The instantaneous power in a three-phase system is defined as
p vi vi vi
aa bb cc
= + + . (2)
Substituting the inverse transform from (1) into (2) we get
p v i v i v i v i v i v i v i
a a a a a a a a a a a a a
= + + = + + =
0 0 1 2 2 1 0 0 1 1 1 1 0
* *
( )
a a a
v i
0 1 1
2 + Re
*
.
(3)
Reference Voltage Generation for DVR: The proposed voltage
regulation scheme is shown in Figure 1. This consists of the following:
l
DVR: represented by voltage sources v
fa
, v
fb
, and v
fc
;
l
Supply voltage: represented by sources v
sa
, v
sb
, and v
sc
.
The DVR is connected between a terminal bus on the left and a load
bus on the right. The voltage sources are connected to the DVR termi-
nals by a feeder with an impedance R jX + . We shall assume that the
loads are balanced and the load impedance is given by Z R jX
l l l
= + .
The incoming bus of the DVR is referred to as the terminal bus while
the outgoing bus is referred to as the load bus with their respective
quantities being denoted by subscripts t and l, respectively.
It is convenient that the DVR reference voltages are generated based
on the measurement of the local variables only. In addition, we stipulate
that the DVR does not supply (or consume) any real power in the steady
state. Since the desired load voltages are balanced sinusoids and the
load is balanced, the instantaneous load power is constant and this must
be equal to the average power entering the DVR terminal bus. Thus
from (3) we get
( ) ( ) p v i v i p
l la sa la sa vla isa tav
= = - = 2 2
1 1 1 1 1 1
Re
*
cos θ θ
(4)
IEEE Power Engineering Review, January 2002 0272-1724/02/$17.00©2002 IEEE 63
Figure 1. Schematic diagram of a DVR connected power system
Figure 2. Phasor diagram of DVR compensation with (a) lagging load and (b)
resistive load