2566 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 8, AUGUST 2011 Trends in Submicrometer InP-Based HBT Architecture Targeting Thermal Management Brice Grandchamp, Virginie Nodjiadjim, Mohammed Zaknoune, Gilles A. Koné, Cyril Hainaut, Jean Godin, Muriel Riet, Thomas Zimmer, Senior Member, IEEE, and Cristell Maneux Abstract—More than ever, thermal management in InP-based heterojunction bipolar transistors (HBTs) is a critical issue since high junction temperature degrades transport properties and de- vice reliability. This paper presents investigation results on the impact of device architecture enhancements aimed at reducing thermal resistance using alternative substrates or passivation ma- terials or metallic collectors or all of them. Using 3-D scalable technology computer-aided design electrothermal simulations, the impact of these features is quantified. This prospective work is based on calibration measurements performed on InP bulk HBTs with various InGaAs subcollector thickness values. A wafer- bonded Si-substrate, a 25-nm-thin InGaAs subcollector, and SiN passivation are the key technological features that reduce the thermal resistance by 70%. An even more aggressive thermal management architecture using metallic collectors reduces the thermal resistance up to 80%. Index Terms—InP heterojunction bipolar transistor (HBT), technology computer-aided design (TCAD), thermal management, thermal resistance, wafer bonding, 3-D simulation. I. I NTRODUCTION P ROVIDING high speed and large breakdown voltage, an InP/InGaAs double heterojunction bipolar transistor (DHBT) is the most suitable choice for high-bit-rate optical communication up to 107 Gb/s [1], [2]. To improve device performance up to 160 Gb/s, the device design modifications imply a larger current density and, consequently, a larger inner temperature [3]. The increasing device temperature has two undesired effects. First, it limits electrical device performance through thermal instability [4], and second, increasing self- heating effects lead to early failure of the device and a shorter lifetime [5]. This paper is focused on the description of self-heating effects for different device architectures using electrother- mal simulations with the technology computer-aided design (TCAD) simulator Sdevice [6]. Calibrated physical models, Manuscript received September 8, 2010; revised March 23, 2011 and April 26, 2011; accepted April 26, 2011. Date of publication May 27, 2011; date of current version July 22, 2011. The review of this paper was arranged by Editor S. Bandyopadhyay. B. Grandchamp, G. A. Koné, C. Hainaut, T. Zimmer, and C. Maneux are with Université de Bordeaux, Integration du Matériau au Système, Centre National de la Recherche Scientifique, Unités Mixtes de Recherche 5218, 33405 Talence, France (e-mail: brice.grandchamp@ims-bordeaux.fr). V. Nodjiadjim, J. Godin, and M. Riet are with Alcatel-Thales III–V Lab, Route de Nozay, F-91461 Marcoussis, Cedex-France. M. Zaknoune is with the Institute of Electronics, Microelectronics, and Nanotechnology, Centre National de la Recherche Scientifique, Unités Mixtes de Recherche 8520, 59652 Villeneuve d’Ascq, France. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2150224 Fig. 1. Thermal resistance levels of InP-based DHBT as a function of emitter area from various bibliographic sources. together with a precise description of the 3-D device structure, allow reproducing the geometrical dependence of the thermal resistance. Thereafter, technological solutions aimed at reduc- ing thermal resistance are considered and evaluated. Such an evaluation has also been partially undertaken by Li et al. [7] and Grandchamp et al. [8] but has been restricted to the resolution of the heat equation to evaluate the thermal resistance. To get more realistic results, electrothermal simulations have been considered in this paper with the purpose to correctly simulate the dissipated power and precisely reproduce the temperature distribution throughout the lattice. Fig. 1 shows the thermal resistance levels of InP/InGaAs DHBTs found in the literature as a function of emitter area. These technologies feature similar epitaxial layers and device processes. This figure illustrates the major issue of self-heating in the submicrometer InP/InGaAs HBT. The thinning of base and collector layers, which is required to reduce transit time, leads to a reduction of the junction surfaces in order to keep the charging term as low as possible while increasing the current density to maintain a high bandwidth [13]. As both dissipated power and thermal resistance increase (resulting from the junc- tion area reduction), self-heating management has become the major issue of further HBT process development. The first problem due to increasing junction temperature is the degrada- tion of electrical performance. As it is enlightened in [3], major material properties are strongly temperature dependent. This is particularly the case for transport parameters such as saturation velocity and carrier mobility. The second problem is reliability related. Indeed, increasing junction temperature has a negative impact on the device lifetime [5], [12]. Most of the degradation 0018-9383/$26.00 © 2011 IEEE