IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS 1 An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth Modulation Min Park, Member, IEEE, Michael H. Perrott, Member, IEEE, and Robert Bogdan Staszewski, Fellow, IEEE Abstract—We propose a time-domain technique that signifi- cantly improves resolution of an RF-DAC. As an alternative to resorting to various resolution improvement attempts in the am- plitude domain or through quantization noise shaping, pulsewidth modulation (PWM) of a single unit switching device is employed with fine timing accuracy easily afforded by advanced CMOS technology. The PWM is categorized into centered PWM and noncentered PWM depending on the relative pulse position, and their performance and implementation methods are compared. The technique is examined in the context of a commercial EDGE polar transmitter realized in 65 nm CMOS, which employs an amplitude modulator with basic 10-bit amplitude resolution lim- ited by the RF-DAC switching device mismatches. The proposed architectures with centered PWM and noncentered PWM achieve the worst case resolution improvement of 2.2 bits and 2.5 bits, respectively, assuming 20-ps worst case time granularity of the PWM signal controls. Index Terms—Amplitude modulation (AM), Enhanced data rate for GSM evolution (EDGE), envelope modulation, polar transmitter, pulsewidth modulation (PWM), RF-DAC. I. INTRODUCTION D IGITAL functionality is crucial nowadays for most wire- less applications. For low-cost and low-power wireless devices, system-on-chip (SoC) integration of RF circuits with digital circuits would be ideal. Some recent publications on RF transmitters have shown that employing an RF-DAC can make RF SoC implementation easier [1]–[4]. Among them, the com- mercial single-chip GSM/EDGE transceiver in [1], [2] is unique in that it uses a simple array of unit-weighted transistor switches to control the output RF amplitude, which operates as near- class-E power amplifier, instead of using a traditional current- source based DAC structure. Fig. 1 illustrates the polar transmitter introduced in [1], [2]. The I/Q baseband data is converted into digital amplitude modulation (AM) and phase/frequency modulation (PM/FM) signals. The frequency signal is fed into the DCO-based -bit digital-to-frequency converter (DFC), which generates Manuscript received October 31, 2010; revised March 03, 2011 and March 11, 2011 accepted March 14, 2011. This paper was recommended by Associate Editor A. Neviani. M. Park is with Maxim Integrated Products, Sunnyvale, CA 94086 USA (e-mail: Min.Park@maxim-ic.com). M. H. Perrott is with the Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates (e-mail: mhperrott@gmail.com). R. B. Staszewski is with the Department of Microelectronics/Delft Institute of Microelectronics and Submicron Technology (DIMES), Faculty of Informa- tion Technology and Systems, Delft University of Technology, 2628 Delft, The Netherlands (e-mail: r.b.staszewski@tudelft.nl). Digital Object Identifier 10.1109/TCSI.2011.2143030 Fig. 1. A polar transmitter based on a DCO and DPA circuits from [2]. For simplicity, the all-digital PLL around the DCO is not shown. a digital phase-modulated RF carrier by means of an all-dig- ital PLL (ADPLL). The amplitude signal drives the -bit digital-to-RF-amplitude converter (DRAC), which includes a digitally controlled power amplifier (DPA). The DPA controls the envelope of the phase-modulated RF carrier; hence it is considered an RF-DAC. The DPA is different from the traditional RF-DACs in [3] or [4], because it does not use current sources. Therefore, the DPA is more compatible with low-voltage and low-cost digital CMOS processes than the tra- ditional RF-DAC. Lack of current sources in the DPA results in a somewhat compressed transfer function, but the look-up-table (LUT) for AM-AM and AM-PM predistortion in the amplitude signal path shown in Fig. 1 linearizes the DPA transfer function. References [1] and [2] have proved that the architecture in Fig. 1 is feasible for SoC meeting all GSM and EDGE specifica- tions. However, the resolution of the amplitude modulation path is limited by lithography and RF mismatches (i.e., both ampli- tude and phase/delay) of the unit switching devices in the DPA, and, consequently, the polar transmitter has little margin in the far-out (i.e., the associated RX band) noise requirement of the SAW-less operation for EDGE. The amplitude resolution could be improved by dithering of the unit transistor switches [1]–[3]. However, the quantization noise is pushed to higher frequencies where emission require- ments might sometimes be difficult to satisfy, especially when considering radio coexistence in a wireless connectivity (e.g., Bluetooth, WLAN) or in a multicore RF-SoC environment. In this paper, we address the far-out noise issue and make the digitally intensive polar architecture of Fig. 1 more attrac- tive to multicore RF integration as well as to advanced modula- tion standards. We propose an RF-DAC structure in which sig- nificant resolution improvement is achieved by means of incre- mental pulsewidth modulation (PWM). In other words, we will improve the resolution by adding a PWM-driven unit switching device on top of the existing RF-DAC structure instead of em- ploying full-PWM. PWM is a time-domain operation since the signal is carried in width or duration of a pulse, which is time- 1549-8328/$26.00 © 2011 IEEE