ARTICLES PUBLISHED ONLINE: 8 NOVEMBER 2009 | DOI: 10.1038/NMAT2570 Large modulation of carrier transport by grain-boundary molecular packing and microstructure in organic thin films Jonathan Rivnay 1 , Leslie H. Jimison 1 , John E. Northrup 2 , Michael F. Toney 3 , Rodrigo Noriega 4 , Shaofeng Lu 5 , Tobin J. Marks 6 , Antonio Facchetti 5,6 and Alberto Salleo 1 * Solution-processable organic semiconductors are central to developing viable printed electronics, and performance comparable to that of amorphous silicon has been reported for films grown from soluble semiconductors. However, the seemingly desirable formation of large crystalline domains introduces grain boundaries, resulting in substantial device-to-device performance variations. Indeed, for films where the grain-boundary structure is random, a few unfavourable grain boundaries may dominate device performance. Here we isolate the effects of molecular-level structure at grain boundaries by engineering the microstructure of the high-performance n-type perylenediimide semiconductor PDI8–CN 2 and analyse their consequences for charge transport. A combination of advanced X-ray scattering, first-principles computation and transistor characterization applied to PDI8–CN 2 films reveals that grain-boundary orientation modulates carrier mobility by approximately two orders of magnitude. For PDI8–CN 2 we show that the molecular packing motif (that is, herringbone versus slip-stacked) plays a decisive part in grain-boundary-induced transport anisotropy. The results of this study provide important guidelines for designing device-optimized molecular semiconductors. S olution-processable small-molecule organic semiconductors have attracted recent scientific and technological interest because of their excellent film-forming properties and field- effect mobilities approaching those of amorphous silicon 1–5 . As it is widely believed that grain boundaries impede transport, much effort has been devoted to producing small-molecule films with large grain sizes from solution 6,7 . However, as the grain size approaches the device size, transistor performance often varies widely from device to device, adversely affecting reproducibility. This behaviour is poorly understood, but suggests that a few grain boundaries can severely compromise overall device performance. The uncontrolled grain boundaries probably lead to large device- to-device variations in the trap energies and densities associated with different types of grain boundary. Charge trapping in the grain boundaries of inorganic semiconductors, such as polycrystalline silicon, has been well studied and can be addressed by passivation, grain-size control and engineered morphologies 8 ; these effects are now well understood, driven largely by the needs of the integrated circuit industry. Grain boundaries and defects are also known to affect optoelectronic materials properties at the meso- and macroscale. For example, packing imperfections and stacking faults introduce optical trap-like tail states in photonic-bandgap materials 9,10 such as colloidal crystals and well-ordered block copolymers. However, in molecular semiconductors, the adverse effects of grain boundaries are not well understood and are complicated by low molecular symmetry, difficult single-crystal growth and weak intermolecular interactions, which promote greater disorder between crystalline regions. Generalizable design rules to control grain boundaries in molec- ular and macromolecular devices have been elusive owing to 1 Department of Materials Science and Engineering, Stanford University, Stanford, California 94305, USA, 2 Palo Alto Research Center (PARC), Palo Alto, California 94304, USA, 3 Stanford Synchrotron Radiation Lightsource, Menlo Park, California 94025, USA, 4 Department of Applied Physics, Stanford University, Stanford, California 94305, USA, 5 Polyera Corporation, Skokie, Illinois 60077, USA, 6 Department of Chemistry, Northwestern University, Evanston, Illinois 60208, USA. *e-mail: asalleo@stanford.edu. the great diversity of materials, morphologies and performance characteristics. In polymer films, grain boundaries can be bridged by macromolecular chains shared by adjacent crystalline grains 11–13 , thereby imparting electrical connectivity and presumably re- ducing barriers to transport. In contrast, grain boundaries in small-molecule films are necessarily spatially sharp or abrupt, and the voltage drops across electrically biased grain boundaries in these films are likely to be substantial 14,15 . Hence, grain-boundary effects on charge transport are large, and, as a result, large variations in charge carrier mobility, transport activation energy 16 , threshold voltage and degradation rate 17 are observed. By controlling their location and orientation with respect to the charge transport direction, it should be possible to quantitatively analyse the penal- ties associated with transport through different grain boundaries. Understanding relationships between film morphology and elec- trical performance should in turn provide correlations between molecular structure, film microstructure and device performance 18 . Here, we formulate design rules: we show that molecular packing plays a key part in determining how different grain-boundary types affect charge transport. We present evidence that the basic pack- ing motif, that is, slip-stack versus herringbone (defined below), strongly influences grain-boundary-induced mobility variations. In slip-stacked materials, we show that grain-boundary effects can dominate film behaviour and that transport between poorly oriented grains is nearly 100 times less efficient than that across low-angle grain boundaries. At a qualitative level of understanding, controlling grain structure in structurally anisotropic molecular materials is known to enhance transport in specific directions. Such aligned small- molecule films can be grown on rubbed dielectric substrates 19 952 NATURE MATERIALS | VOL 8 | DECEMBER 2009 | www.nature.com/naturematerials