K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy + , Xiang Lu * , Zhuo Li * , Weiping Shi * , Hari Balachandran + Dept. of Computer Science Texas A&M University College Station TX 77843-3112 Tel: (979) 862-4387 Fax: (979) 847-8578 Email: walker@cs.tamu.edu * Dept. of Electrical Engineering Texas A&M University College Station TX 77843-3124 Tel: (979) 458-0093 Fax: (979) 845-2630 Email: wshi@ee.tamu.edu + Texas Instruments, Inc. 12500 TI Boulevard MS 8761 Dallas TX 75243 Tel: (214) 480-3783 Fax: (214) 480-3449 Email: {d-reddy2, harib}@ti.com Abstract To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Existing test generation tools are inefficient in automatically identifying the longest testable paths due to the high computational complexity. In this work a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The two strategies are compared and the test generation efficiency is evaluated on ISCAS89 benchmark circuits and industrial designs. Experiments show that testing transition faults through the longest paths can be done in reasonable test set size. 1. Introduction Delay test has been investigated for many years. At- speed test significantly increases the delay fault coverage in industrial applications. The transition fault model [1], which is the simplest delay fault model, is usually used in these applications. However, the transition fault model targets large delay faults which cause all the sensitizable paths through the fault site to be slow. Recent research shows that resistive opens are one of the major defect types which cause delay faults [2], and that small delay faults cannot be neglected [3]. To detect the smallest delay fault at a fault site, the longest sensitizable paths through it must be tested. But (longest) path delay fault test generation is much more expensive than transition fault test generation, because a transition fault test can be composed by pairing stuck-at-0 and stuck-at-1 vectors [4] and transition fault test generation for sequential circuits has been extensively investigated [5][6][7]. Recently some research significantly decreased the cost of path delay fault test generation [8][9] and these methodologies are able to integrate some path selection criteria, such as the longest paths through each line. However, they assume the circuits are combinational, i.e. there is no dependence between the two test vectors or between two bits within a vector. These methodologies cannot be applied to sequential circuits directly. The reason is that the commonly-used design-for-testability (DFT) structures, such as muxed scan, rarely support combinational enhanced-scan, which allows the two vectors to be independent but requires more silicon area and introduces more delay. Therefore, a new automatic test pattern generation (ATPG) tool for path delay faults in sequential circuits has to be developed, to target practical DFT structures. The ATPG was developed by extending a path generation algorithm for combinational circuits [9] to handle scan-based synchronous sequential circuits. This tool is able to generate K longest paths through the input and output pins of each gate (KLPG) for both slow-to-rise and slow-to-fall faults. In this work test generation is limited to K=1 because it is assumed the industry cannot afford a test set much larger than a transition fault test set. At speed testing that utilizes scan, often called AC scan, uses two common approaches, “launch-on-shift” and “launch-on-capture”. The constraints from these approaches result in sequential false paths [10] which are combinationally testable. The delays of the longest combinational and sequential testable paths through each line are compared in the experiments. The remainder of the paper is organized as follows. Section 2 introduces the two practical test approaches to apply at-speed test in a scan-based circuit. Section 3 describes the test generation algorithm using the two approaches. Section 4 includes experimental results on the ISCAS89 benchmark circuits and industrial designs. Section 5 concludes with directions for future research. 2. Scan-Based At-Speed Test Approaches In low-cost automatic test equipment (ATE), the test speed is usually much slower than the functional speed of the circuit under test. This is not a problem to test stuck-at and large delay faults, but small delay faults may escape. Therefore at-speed test is preferred to increase the realistic delay fault coverage. However, due to the low-cost ATE speed limitation, the at-speed tests primarily in use in industry are built-in self-test (BIST) and AC scan. Evidence has shown that BIST can achieve very high fault coverage for stuck-at and transition faults [11], but it has low probability to sensitize enough critical paths, e.g. the longest path through each line. On the other hand, functional tests running at full speed are becoming unattractive due to the high cost of development and application [12]. Therefore, this paper focuses on high-quality delay test generation using existing scan designs. ITC INTERNATIONAL TEST CONFERENCE 0-7803-8580-2/04 $20.00 Copyright 2004 IEEE Paper 9.2 223