IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 10, OCTOBER 2007 2669 OFF -State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown Dhanoop Varghese, Student Member, IEEE, Haldun Kufluoglu, Student Member, IEEE, Vijay Reddy, Hisashi Shichijo, Dan Mosher, Member, IEEE, Srikanth Krishnan, Associate Member, IEEE, and Muhammad Ashraful Alam, Fellow, IEEE Abstract—OFF-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and well- calibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during OFF-state stress. Classical ON-state hot carrier degradation has historically been associated with broken ≡ Si–H bonds at the Si/SiO 2 interface. In contrast, the OFF-state degradation in drain-extended devices is shown to be due to broken ≡ Si–O– bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on short- term stress data. Time evolution of degradation due to broken ≡ Si–O– bonds and the resultant universal behavior is ex- plained by a bond-dispersion model. Finally, we show that, under OFF-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric break- down time, as both of them are driven by broken ≡ Si–O– bonds. Index Terms—Bond-dispersion (B-D) model, drain-extended devices, gate dielectric breakdown, hot carrier degradation, interface damage, OFF-state degradation, Si–O bonds, universal degradation. I. INTRODUCTION T HE DEVICE dimension and supply voltage for the core logic and memory transistors have been scaled down sys- tematically over the last few decades. This, however, is not the case for input/output (IO) devices (e.g., LDMOS, DeMOS, etc. [1]–[3]) that interface ICs to the outside world and, therefore, must continue to operate at supply voltages higher than that of core transistors. Such high operating biases often lead to unique reliability issues which are different from the core transistors and which cannot be understood in terms of uncorrelated combinations of classical theories of NBTI, hot carrier injec- tion (HCI), or time-dependent dielectric breakdown (TDDB) [4], [5]. This makes the lifetime estimations of IO transistors particularly difficult and sometimes overly conservative. Manuscript received April 24, 2007; revised June 26, 2007. The review of this paper was arranged by Editor J. Suehle. D. Varghese, H. Kufluoglu, and M. A. Alam are with Purdue University, West Lafayette, IN 47907 USA (e-mail: dvarghe@purdue.edu). V. Reddy, H. Shichijo, D. Mosher, and S. Krishnan are with the Texas Instruments Inc., Dallas, TX 75243 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2007.904587 Hot carrier degradation (HCI) has been a major issue for core transistors since the early 1980s, when the device dimensions started shrinking while the supply voltage (V DD ) remained at 5 V [6]. However, HCI is a voltage-driven (but not a field driven) phenomenon; therefore, by mid 1990s, it ceased being a dominant degradation mode as V DD was scaled down from 5 V. Classical hot carrier is an extensively studied topic, with the following well-known characteristics: 1) Hot carriers that are responsible for the damage are due to impact ionization (II) of source current, and the degradation is found to maximize at peak substrate current (I B ) stress conditions (V G ≈ V D /2) corresponding to peak hot carrier generation [7]–[11]. 2) Inter- face damage during the stress is known to have a power law behavior (ΔN IT = At n ), with the time exponent n close to 0.5 [11]–[14]. 3) A fraction of damage that is generated during classical hot carrier stress is found to recover on the removal of the stress conditions [13], [14]. 4) The degradation is believed to be due to broken ≡ Si–H bonds at the Si/SiO 2 interface, as confirmed by the isotope effect observed during the stress [11], [15]. 5) The classical hot carrier degradation shows no cor- relation with the dielectric breakdown (TDDB, [16]–[18]), pre- sumably because TDDB results from broken ≡ Si–O– bonds. However, some recent reports show that oxide degradation can indeed occur during hot carrier stress conditions [19], [20]. In this paper (expanded version of the study in [21]), we study the reliability of drain-extended NMOS (DeNMOS) tran- sistors subjected to OFF-state hot carrier stress (V G = 0 V, V D > 5 V), and we find that the characteristics of this degra- dation are distinct and unique compared to classical ON-state HCI. It has been hypothesized that an interface damage during OFF-state operation is due to generation of hot carriers by the high electric field localized near the drain end, and their subsequent injection into the gate oxide. However, unlike the classical ON-state hot carrier degradation where hot carriers are generated by the II of source current, the source current that flows in OFF-state is just the subthreshold leakage and might not be a significant source for hot carriers. Second, the interface trap generation during OFF-state degradation is found to have high time exponents (n ≈ 0.7–0.8), which are higher compared to that obtained during classical ON-state studies (n ≈ 0.5). In addition, unlike the classical ON-state hot carrier stress, the interface traps that are generated during the OFF-state stress do not recover on the removal of the stress 0018-9383/$25.00 © 2007 IEEE