A comprehensive model for PMOS NBTI degradation: Recent progress M.A. Alam a, * , H. Kufluoglu a , D. Varghese a,b , S. Mahapatra b a Purdue University, West Lafayette, IN 47906, USA b Department of Electrical Engineering, IIT Bombay, Mumbai 400076, India Received 24 May 2006; received in revised form 8 September 2006 Available online 13 December 2006 Abstract Negative bias temperature instability (NBTI) is a well-known reliability concern for PMOS transistors. We review the literature to find seven key experimental features of NBTI degradation. These features appear mutually inconsistent and have often defied easy inter- pretation. By reformulating the Reaction–Diffusion model in a particularly simple form, we show that these seven apparently contradic- tory features of NBTI actually reflect different facets of the same underlying physical mechanism. Ó 2006 Elsevier Ltd. All rights reserved. 1. Background Design of any digital circuit is based on the presumption that transistor parameters will remain bounded by a certain margin (typically ±15%) during the projected lifetime of the IC. This margin consists of initial manufacturing tolerance encapsulated in C K P numbers as well as other time-dependent parameter shifts due to various transistor degradation mechanisms like hot carrier degradation (HCI), gate dielectric breakdown (TDDB), negative bias temperature instability (NBTI), etc. Among them, NBTI has been a persistent (and perhaps most significant) reli- ability concern for CMOS technology generations below 130 nm node [1–8]. Two factors – increasing oxide field (to enhance transistor performance without scaling gate oxide) and the use of oxynitrides (to prevent Boron pene- tration and to reduce gate leakage) [9,10] – appear to have exacerbated this PMOS-specific reliability issue. Specifi- cally, NBTI causes systematic reduction in transistor parameters (e.g., drain current, transconductance, thresh- old voltage, capacitance, etc.) when a PMOSFET is biased in inversion (V S = V D = V B = V DD and V G = 0). Since this NBTI-specific biasing condition arises universally in inverting logic, SRAM cells, I/O system, dynamic logic, etc. [11–13], it is not surprising that the concern about NBTI is pervasive in the semiconductor industry. Since NBTI has been a reliability concern from the very early days of integrated circuits in mid 1960s [14,15], there are many reports on various aspects of NBTI degradation over the last 40 years [3]. An extensive review of the state- of-art of the pre-2003 experimental results and the possible theoretical foundations has been made in our previous arti- cle in Microelectronics Reliability [1]. After correcting for artifacts arising from incorrect stress condition leading to spuriously high degradation exponent at later stages of degradation, resolving controversies involving oxide field vs. gate voltage dependence, and addressing process spe- cific NBTI degradation issues, the essence and consensus regarding NBTI phenomena until 2002–2003 can be sum- marized as follows: (1) The degradation is field-driven and is related to inter- face traps at the Si/SiO 2 interface [4]. (2) Threshold voltage degradation due to NBTI is given by DV T  A exp(nE D /kT)t n with n  0.25 (see Fig. 1) and E D  0.5 eV [1,4,6]. (3) Once NBTI stress is removed, a fraction of interface traps can self-anneal [6,16–18]. None of the pre-2003 reports, however, seemed to have realized that the values of n and E D of NBTI 0026-2714/$ - see front matter Ó 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2006.10.012 * Corresponding author. E-mail address: alam@purdue.edu (M.A. Alam). www.elsevier.com/locate/microrel Microelectronics Reliability 47 (2007) 853–862