This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON ADVANCED PACKAGING 1 Modeling and Analysis of High-Speed I/O Links Ganesh Balamurugan, Member, IEEE, Bryan Casper, James E. Jaussi, Member, IEEE, Mozhgan Mansuri, Frank O’Mahony, and Joseph Kennedy, Member, IEEE Abstract—Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A com- putationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topolo- gies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design. Index Terms—High-speed I/O, I/O power optimization, link analysis tools, signaling analysis, statistical signaling analysis. I. INTRODUCTION O VER the past decade, high-speed input/output (I/O) data rates have scaled from a few hundred Mb/s to . This has been possible due to improvements in link architecture (e.g., point-to-point instead of multidrop), signaling methods (e.g., transmit pre-emphasis), circuits (e.g., low noise receivers and precision clocking), and semiconductor process technology. A typical multi-Gb/s I/O link today (e.g., [1]–[3]) includes several of the components shown in Fig. 1: equalizers at TX/RX to compensate for channel intersymbol interference (ISI), high-speed clock generation/distribution circuits, and clock-data recovery (CDR) circuits to optimally sample the incoming data. This increased complexity has required significant improvements in link modeling and anal- ysis techniques to enable design optimization and validation. Advanced signaling analysis tools are also used today to help draft I/O standards and specifications. By comprehensively modeling both the circuits and interconnect in a high-speed link, these tools enable system level co-optimization of channel components, link architecture and low level circuits. In the past, link analysis was based on empirical simulations or worst-case analysis. In the former approach, a transient anal- ysis was done using a circuit/interconnect simulator to com- Manuscript received June 27, 2008; revised November 22, 2008. This work was recommended for publication by Associate Editor W. Beyene upon evalu- ation of the reviewers comments. The authors are with the Microprocessor Technology Laboratories, Intel Cor- poration, Hillsboro, OR 97124 USA (e-mail: ganesh.balamurugan@intel.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TADVP.2008.2011366 Fig. 1. Components of a high-speed I/O link. pute performance margins from the receiver eye obtained with a few thousand bits. With increasing link complexity (as shown in Fig. 1) and the strong interaction between various link com- ponents (e.g., channel characteristics and CDR performance), it is impractical to model the entire link using a SPICE-like time domain simulator. Since it is not possible to increase the number of bits used in the simulation to validate the low BERs needed in links today ( ), it is difficult to predict performance margins with any certainty using a solely empirical method. Worst-case link analysis methods (e.g., peak distortion analysis in [4], [5]) circumvent the need for time consuming simulations by analytically determining the worst-case eye from the channel response and noise models. While these methods are useful for applications like equalizer optimization due to their computa- tional simplicity [6], they are not suited to high-speed link per- formance analysis. This is because the results of a worst-case analysis in which the worst-case effects of several noise and in- terference sources are simply superimposed can be highly pes- simistic (this is especially true when modulation schemes more complex than NRZ are used). Due to these drawbacks of empir- ical and worst-case analysis methods, almost all link analysis tools used today (e.g., [7]–[9]) are statistical in nature. Statistical link analysis attempts to account for all relevant noise and interference sources in a probabilistic fashion to derive statistical performance metrics like BER analytically, without extensive behavioral/circuit simulations. With appro- priate models for various link components, this type of analysis enables computationally efficient validation and performance characterization for very low target BERs ( ). In this paper, we present models for various key blocks in a high-speed link and techniques to use them for statistical link analysis. 1521-3323/$25.00 © 2009 IEEE Authorized licensed use limited to: University of Illinois. Downloaded on April 9, 2009 at 13:04 from IEEE Xplore. Restrictions apply.