V
BIAS
I
BIAS2
V
out
V
in
M
1
M
2
V
A
V
B
V
BIAS1
I
BIAS1
I
BIAS2
M
P
V
out
V
CTRL
V
in
GND
M
14
M
15
V
BIAS2
C
a
M
16
Cascode current source
R
S
V
1
V
2
V
3
GND
M
P
I
BIAS1
V
CTRL
(a) (c)
M
P
M
C
I
N
C
L
R
esr
I
L
V
out
(b)
V
in
V
CTRL
Fig. 1. (a) The schematic of FVF based STC-LDO regulator
[1]
(b) The conventional CAFVF based LDO regulators structure
[3,4]
, (c) the proposed OCL-
CAFVF LDO regulator structure.
Cascoded Flipped Voltage Follower Based Output-
Capacitorless Low-Dropout Regulator for SoCs
Guangxiang Li
1
, Jianping Guo
1, 2
, Yanqi Zheng
1, 2
, Mo Huang
3
, Dihu Chen
1, 2
1
School of Physics and Engineering, Sun Yat-sen University, Guangzhou, China
2
SYSU-CMU Shunde International Joint Research Institute, Foshan, China
3
State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China
Email: guojp3@mail.sysu.edu.cn
Abstract—A novel cascoded flipped voltage follower (CAFVF)
based output-capacitorless low-dropout (LDO) regulator is
proposed and implemented in 0.18-Pm CMOS technology. With
a cascode current source (CCS) embedded into the CAFVF
structure, the proposed LDO regulator achieves 58.6-dB DC gain
in heavy loading condition (100 mA), which is 44-dB for the
conventional CAFVF counterpart under identical conditions.
The cascode compensation technique is introduced to widen the
loop bandwidth and reduce the minimal loading requirement.
With a 5-pF compensation capacitor, the minimum load current
to keep the proposed LDO regulator stable is reduced to 50 PA.
In addition, the unity-gain frequency (UGF) is extended from
1.51 MHz to 2.36 MHz in 100-mA loading condition. Moreover,
an accurate stability analysis without ignoring any channel
resistance has been presented in this work. Simulation results
show that the LDO regulator consumes an ultra-low quiescent
current (Iq) of 14 μA for input voltage ranging from 1.2 V to 1.8
V, with a dropout voltage (Vdrop) of 200 mV.
Keywords—Capacitorless, low-dropout (LDO) regulator,
cascoded flipped voltage follower (CAFVF), cascode compensation.
I. INTRODUCTION
Low-dropout (LDO) regulator is a low-cost power-
management solution for system-on-a-chip (SoC) applications.
Compared with the previous LDO architecture, the single-
transistor-control (STC) LDO regulator based on the flipped
voltage follower (FVF) cell, as shown in Fig. 1(a) [1], has
recently drawn significant attentions for its simplicity and fast
transient response [2]. However, STC-LDO regulator suffers a
low loop gain and thus poor regulation due to its simple folded
structure. In addition, it has the minimum biasing or loading
requirement for stability and regulation accuracy issues.
To solve both of the stated problems, LDO regulators based
on the cascoded flipped voltage follower (CAFVF), which is
an improved version of FVF, has been proposed [3, 4]. As
shown in Fig. 1(b), compared with FVF based STC-LDO
regulator, the CAFVF LDO regulator has added another
NMOS (M2) to form a folded cascode amplifier structure. The
added M2 dictates VA to VBIASVGS,M2. As a result, M1 is ensured
to work in saturation region even with a small biasing or load
current. Therefore, the CAFVF LDO has alleviated the
minimum biasing or loading requirement faced by FVF based
STC-LDO regulator. Moreover, the transistor M2 serves as a
common-gate gain stage, providing extra voltage gain in the
feedback loop. Thus, the load regulation will be enhanced. To
further increase the loop gain, an additional common-source
978-1-4673-9094-1/15/$31.00 ©2015 IEEE 368