IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012 3639 Design and Tuning of a Modified Power-Based PLL for Single-Phase Grid-Connected Power Conditioning Systems Saeed Golestan, Member, IEEE, Mohammad Monfared, Member, IEEE, Francisco D. Freijedo, Member, IEEE, and Josep M. Guerrero, Senior Member, IEEE Abstract—One of the most important aspects for the proper op- eration of the single-phase grid-tied power-conditioning systems is the synchronization with the utility grid. Among various synchro- nization techniques, phase locked loop (PLL)-based algorithms have found a lot of interest for the advantages they present. Typ- ically, the single-phase PLLs use a sinusoidal multiplier as the phase detector (PD). These PLLs are generally referred to as the power-based PLL (pPLL). In this paper, the drawbacks associated with the pPLL technique (i.e., the sensitivity to the grid voltage variations, and the double-frequency oscillations that appear in the estimated phase/frequency) are discussed in detail, and some of the previously reported solutions are examined. Then, to over- come these drawbacks, a simple and effective technique, called the double-frequency and amplitude compensation (DFAC) method is proposed. The effectiveness of the proposed method is evalu- ated through a detailed mathematical analysis. A systematic design method to fine-tune the PLL parameters is then suggested, which guarantees a fast transient response, a high disturbance rejection capability, and a robust performance. Finally, the simulation and experimental results are presented, which highlight the effective- ness of the proposed PLL. Index Terms—Frequency estimation, phase estimation, phase- locked loop (PLL), power-based PLL (pPLL), single phase grid- connected converters, synchronization. I. INTRODUCTION T HE phase-angle and frequency of the utility grid are vi- tal information for most single-phase grid-tied power- conditioning systems, such as active power filters [1], dynamic voltage restorers [2], [3], flexible ac transmission systems Manuscript received September 20, 2011; revised December 2, 2011; ac- cepted January 2, 2012. Date of current version April 20, 2012. This work was supported in part by the Abadan Branch-Islamic Azad University under Inno- vative Research Scheme. Recommended for publication by Associate Editor B. Wu. S. Golestan is with the Department of Electrical Engineering, Abadan Branch, Islamic Azad University, Abadan 63178-36531, Iran (e-mail: s.golestan@ieee.org). M. Monfared is with the Department of Electrical Engineering, Faculty of Engineering, Ferdowsi University of Mashhad, Mashhad, Iran (e-mail: m.monfared@um.ac.ir). F. D. Freijedo is with the Department of Electronic Technology, Escola T´ ecnica Superior de Enxe˜ neiros Industriais, University of Vigo, Vigo 36200, Spain (e-mail: fdfrei@uvigo.es). J. M. Guerrero is with the Department of Energy Technology, Aalborg Uni- versity, Aalborg DK-9220, Denmark (e-mail: joz@et.aau.dk). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2012.2183894 Fig. 1. Basic scheme of a single-phase PLL. (FACTS) [4]–[6], uninterruptible power supplies (UPS) [7], and distributed power generation and storage systems [8]. To estimate the frequency and phase-angle of the single- phase signals various methods have been proposed in the liter- ature [4]–[25]. Among these techniques, the phase locked loop (PLL)-based algorithms are the most widely accepted ones, due to their simplicity, robustness, and effectiveness [4]–[20]. Fo- cusing on grid-connected power converter applications, a PLL is a closed-loop feedback control system, which synchronizes its output signal in frequency, as well as in phase, with the grid voltage fundamental component. In spite of their differ- ences, all PLL techniques are composed of three basic parts, namely: 1) phase detector (PD), 2) loop filter (LF), and 3) voltage-controlled oscillator, as illustrated in Fig. 1. The main difference among different PLLs usually lies in how the PD block is implemented. Typically, the single-phase PLLs use a sinusoidal multiplier as the PD. These PLLs are generally referred to as the power-based PLL (pPLL). In the fol- lowing section, the drawbacks associated with the pPLL tech- nique (i.e., the sensitivity to the grid voltage variations, and the double-frequency oscillations that appear in the estimated phase/frequency) are discussed in detail, and some of the previ- ously reported solutions are examined. Then, to overcome these drawbacks, a simple and effective technique, called the double- frequency and amplitude compensation (DFAC) method is pro- posed. Through a detailed mathematical analysis it is shown that the proposed DFAC method successfully compensates for the undesired double-frequency oscillations, as well as the in- put voltage amplitude variations, while keeping a fast dynamic response and robust performance for the PLL. It is worth re- marking that, for three-phase PLLs, tackling the generation of the low-order oscillations in the estimated phase/frequency has been well addressed [26], [27]. An accurate tuning of the PLL parameters requires consider- ing several factors such as the stability margin, the disturbance rejection ability, and the transient response to the phase-jump and frequency variation. Some suggestions to design the PLL 0885-8993/$31.00 © 2012 IEEE