Analytical Calculation of the Equivalent Inductance for Signal Vias in Parallel Planes with Arbitrary P/G Via Distribution Gaudencio Hernandez-Sosa and Adan Sanchez System Integration and Adaptivity (SIA) Intel Labs, Guadalajara Design Center Tlaquepaque, Jalisco, México e-mail: gaudencio.hernandez.sosa@intel.com, adan.sanchez@intel.com Abstract—This paper introduces an analytical method for calculating the equivalent inductance associated to signal vias in parallel planes with arbitrary power/ground (P/G) via distribution. The proposal is corroborated by comparing the equivalent inductances predicted by a commercial electromagnetic solver (HFSS) and those predicted by the analytical method. Excellent results are obtained demonstrating the accuracy and validity of the proposal. Keywords- vias, equivalent self inductance, equivalent mutual inductance, high-speed interconnects. I. INTRODUCTION Vias play a key role in the implementation of high-speed links and power distribution networks (PDN) in today’s packages and boards. However, due to the high-density environment in modern packaging, inductive coupling between vias may cause considerable crosstalk problems in the signal distribution network (SDN) and serious voltage fluctuations in the PDN [1]. In this way, the equivalent inductance associated to signal vias and power/ground (P/G) vias becomes a crucial parameter in the design of reliable high-speed chip-to-chip links and PDN. Nowadays, a common practice for characterizing vias in high-density packaging is using commercial electromagnetic (EM) solvers such as HFSS, Q3D, CST, etc and full-wave numerical methods [2]. These EM solvers require three- dimensional (3D) models to solve the Maxwell’s equations in order to extract the corresponding inductances from simulated data. Unfortunately, this approach requires considerable simulation time and computational resources which may be prohibitive in early design stages. Furthermore, simultaneously minimizing undesired effects such as return loss and crosstalk in massively coupled vias is very hard to achieve based on full-wave approaches since it is not straightforward to link the geometry and dimensions of these structures with the corresponding electrical properties. Consequently, the use of EM solvers is not convenient to explore the design space in a systematic and fast manner, especially when the system is highly constrained (in terms of power, area and cost) and when a fast time to market is needed. For this reason, we introduce analytical equations for calculating the equivalent self and mutual inductance associated to signal vias with arbitrary P/G via distribution in high-density packages. The proposal is corroborated by comparing the equivalent inductances predicted by the analytical method and those predicted by the commercial EM solver HFSS. For this purpose, six signal vias sharing two P/G vias inside a parallel-plate cavity was used as test validation example. Furthermore, the computational time and the memory consumption required by both methods were compared in order to show the benefits of the proposal. II. EQUIVALENT INDUCTANCE FOR VIAS Fig. 1 shows N signal vias and M P/G vias inside a cavity formed by a rectangular parallel-plane pair with dimensions x 1 and x 2 . When currents are injected at the signal vias, these currents travel along the signal vias and return through the P/G vias. This originates electromagnetic fields inside the cavity and therefore coupling between adjacent vias. In most practical designs, the dimension of the vias and the separation between the planes are electrically short, even at the highest frequency of interest. Thus, all electromagnetic modes in the cavity will be evanescent below the first resonance frequency and therefore, these can be modeled as self and mutual inductances as shown in Fig. 2. If vias are located away from the edges of the cavity, the following closed-form expressions provided in [3] can be used to find the self and mutual inductances depicted in Fig. 2:       -       + = 75 0 4 ln 2 2 1 0 . , , , a x x h L S l k q p π μ (1) ( )         -         + + = 75 0 4 ln 2 2 1 . , , , , , , , , a s x x d M SG GG SS pk kl pq SG GG SS pk kl pq π μ (2) where a is the via radius and h is the via height. On the other hand,    ,    and    are the separations between the signal via p and q, between P/G via k and l and between signal via p and P/G via k, respectively. Notice that the inductances due to the metal planes are not considered in the circuit model of Fig. 2. However, as demonstrated in [4], the plane inductances do not significantly contribute to the equivalent inductance of signal vias and consequently, these can be neglected. Thus, the currents and voltages across the 2012 8th International Caribbean Conference on Devices, Circuts and Systems (ICCDCS) 978-1-4577-1117-6/12/$26.00 ©2012 IEEE