This paper has been published in Expert Systems with Applications. Reference to this paper should be made as follows: Wu, Jei-Zheng , Chien * , C.-F. (2008/07), “Modeling semiconductor testing job scheduling and dynamic testing machine configuration,” Expert Systems with Applications, 35(1/2):485-496. (http://dx.doi.org/10.1016/j.eswa.2007.07.026 ) 1 Modeling and a genetic algorithm for semiconductor final test scheduling Jei-Zheng Wu and Chen-Fu Chien Abstract The overall flow of the final test of IC devices can be represented by the job shop model with limited simultaneous multiple resources in which various product mixes, jobs recirculation, uncertain arrival of jobs, and unstable processing times complicate the problem. This study proposes a hybrid approach including a mathematical programming model to optimize the testing job scheduling and an algorithm to specify the machine configuration of each job and allocate specific resources. The results of detailed scheduling can be graphically represented as timetables of testing resources in Gantt charts. Furthermore, a genetic algorithm is also developed to solve the problem in a short time for implementation. The experimental results demonstrated viability of the proposed approach. Keywords: Scheduling; Timetabling; Semiconductor final testing; Genetic algorithm 1. Introduction The semiconductor industry has grown rapidly and subsequent production planning problems have raised many important research issues (Lee, Uzsoy, & Martin-Vega, 1992; Leachman, 1993). The semiconductor manufacturing scheduling problem is complicated by various product mixes, jobs recirculation, uncertain arrival of jobs, and unstable processing times. In particular, final testing of IC devices is the final operation in semiconductor manufacturing. The objectives of final test are to deliver passed IC circuits of the required quality on time to customers while using resources efficiently. The overall flow of the final test can be represented by the job shop model with limited resources. Many optimization models or algorithms for short-term production planning at the shop floor level have been developed. However, the manufacturing environment of final test is unstable and uncertain. For example, the machine condition is uncertain affecting the yield rate and the throughput. Hence, the scheduling problem of final test is more complex than the conventional job-shop scheduling problem. Importantly, the testing site is typically the bottleneck of the final test operation because the equipment at the testing