Journal of VLSI Signal Processing 16, 247–276 (1997) c  1997 Kluwer Academic Publishers. Manufactured in The Netherlands. Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits KRIS GAJ, EBY G. FRIEDMAN AND MARC J. FELDMAN Department of Electrical Engineering, University of Rochester, Rochester, New York 14627 Received November 24, 1996; Revised December 18, 1996 Abstract. Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semi- conductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits. This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared. In many circuit topologies of current medium to large scale RSFQ circuits, single-phase synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Syn- chronous clocking of RSFQ circuits at multigigahertz frequencies requires the application of non-standard design techniques such as pipelined clocking and intentional non-zero clock skew. Even with these techniques, there exist difficulties which arise from the deleterious effects of process variations on circuit yield and performance. As a re- sult, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes. 1. Introduction The recent achievements of superconductive circuits using Rapid Single Flux Quantum (RSFQ) logic make this technology a possible candidate to first cross the boundary of 100 GHz clock frequency in a large scale digital circuit. The success of RSFQ circuits is in part due to the unique convention used to represent digital information. Rather than using steady voltage levels, RSFQ circuits use quantized voltage pulses to transmit binary logic state information. This logic scheme has necessarily led to new timing concepts and techniques in order to coordinate the operation of the gates and sub-circuits at multigigahertz fre- quencies. Nevertheless, the similarities to semicon- ductor voltage-state timing are strong, and the two technologies can be discussed in the same language. This paper is written with the intention that both semiconductor and superconductor communities will benefit from the mutual exchange of ideas on the tim- ing of high speed large scale digital circuits. RSFQ de- signers inherit a broad range of techniques and methods developed over many years by VLSI semiconductor circuit designers. The capability of RSFQ technology offers the semiconductor community an opportunity to be made aware about existing pitfalls in the design and