LOW POWER FLEXIBLE RAKE RECEIVERS FOR WCDMA Boris D. Andreev, Edward L. Titlebaum, and Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester Rochester, New York 14627 {bandreev, tbaum, friedman} @ece.rochester.edu Abstract: Two low power flexible Rake receiver architectures are presented. The first architecture exploits the statistical distribution of multipath delays in wireless channels to reduce power dissipation. The second Rake architecture is based on a tradeoff between algorithm accuracy and circuit complexity. By introducing a negligible performance degradation, the SRAM memory for the input sample buffer is eliminated, achieving low power consumption and small silicon area. Both Rake architectures are targeted for third generation WCDMA mobile terminals (downlink receivers), but the circuits can also be applied to base station (uplink) receivers. The architectures have been synthesized in a 0.18 m standard cell CMOS technology using Cadence BuildGates. The proposed architectures achieve significant area and power savings as compared to previous circuits described in the literature. 1 I. INTRODUCTION A Rake receiver is an integral part of a wireless CDMA communication system, combining the received signals from several multipaths into a common decision statistic with significantly improved signal-to-noise ratio (SNR) and robustness to channel fading. A FlexRake architecture is proposed in [1] and shown in Fig. 1. Signal reception is performed with a single correlator engine and a stream buffer storing the entire delay spread of baseband I/Q samples. The primary advantage of the proposed approach is flexible multipath allocation supporting enhanced modularity of the receiver and resource sharing * This research is supported in part by the Semiconductor Research Corporation under Contract No. 2003-TJ-1068, the DARPA/ITO under AFRL Contract F29601-00-K-0182, the National Science Foundation under Contract No. CCR-0304574, the Fulbright Program under Grant No. 87481764, grants from the New York State Office of Science, Technology & Academic Research to the Center for Advanced Technology – Electronic Imaging Systems and to the Microelectronics Design Center, and by grants from Xerox Corporation, IBM Corporation, Intel Corporation, Lucent Technologies Corporation, and Eastman Kodak Company. among multiple channel decoders. A low power alternative of the original FlexRake receiver employing parallel correlation engines for several data channels is presented in [2]. A common drawback of both architectures proposed in [1] and [2] is the significant power and area resources required for the input stream buffer. The efficient memory organization of the sample buffer is the primary focus of this paper. The signals traveling along different multipaths from a transmitter to a wireless receiver can be assumed to have a uniform (or Poisson) delay distribution, such that L multipath signals arrive with equal probability during a time period [0, T max ]. The delay spread T max is discretely represented by N sample = T max /T sample sample moments. Each chip of the received direct sequence CDMA signal is represented by N spc samples (N spc is typically between two and six) produced by an analog-to-digital converter (ADC). Each of the multipath signals is locked on one of N spc samples within each chip and all data chips are despread by the appropriate pseudonoise (PN) code phase to form data bit decision statistics. In a conventional flexible Rake receiver all received input samples are stored in the SRAM memory buffer [1, 2]. The multipath delay information from the channel estimation and signal acquisition and tracking blocks is used to address the individual multipaths in the buffer. An approach for reducing power consumption based on the statistical distribution of the multipath delays is described in section II. A second flexible Rake architecture is proposed in section III, where the SRAM memory block of the input buffer is eliminated, albeit with a minor degradation in algorithm accuracy. Results from the logic synthesis of both architectures are presented in section IV and compared to previous reports. II. REDUCTION OF INPUT BUFFER WRITE ACCESSES The number of SRAM write accesses can be reduced significantly based on the characteristic that the delays of the detected multipath signals are statistically distributed and the probability that all stored samples are used is low. Only a fraction of the stored samples are therefore used in the decoding process. For all cases where L N spc , there is a redundancy in the recorded input samples since no more than L sample slots are needed at a time. For L equally Fig. 1: Architecture of a FlexRake receiver [1] Circular address generator Offset address generator Received I/Q samples Integration registers FIFO symbol buffer Symbol dumps Code generators Stream buffer Correlator engine Sample buffer IV - 97 0-7803-8251-X/04/$17.00 ©2004 IEEE ISCAS 2004 ➠ ➡