IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006 1149 A 1.5-V Multi-Mode Quad-Band RF Receiver for GSM/EDGE/CDMA2K in 90-nm Digital CMOS Process Bertan Bakkaloglu, Member, IEEE, Paul Fontaine, Member, IEEE, Ahmed Nader Mohieldin, Member, IEEE, Solti Peng, Sher Jiun Fang, Member, IEEE, and Fikret Dülger, Member, IEEE Abstract—A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conver- sion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of 8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm . Index Terms—CMOS integrated circuits, low-noise amplifier, multimode, radio frequency integrated circuits, transceivers, wireless. I. INTRODUCTION H IGH DATA-RATE mobile terminals for 3G communi- cation applications need to support more established 2G and 2.5G systems, which demand highly integrated multi-mode receivers on the same system-on-chip (SoC) IC. A conventional approach to address this design problem is to have multiple signal paths in the receiver and multiple upconversion paths for the transmitter [1]. However, for deep-submicron SoC appli- cations, it is critical to utilize silicon area efficiently, therefore RF and baseband signal paths should be shared as much as possible. In this paper, design and implementation of a highly digital multi-mode RF transceiver supporting GSM/PCS/DCS and CDMA2K standards is presented. Fig. 1 shows the top level diagram of the receiver. Several design techniques to address wide dynamic range, low-noise direct-conversion RF front-end Manuscript received September 16, 2005; revised December 10, 2005. B. Bakkaloglu is with the Department of Electrical Engineering, Ira A. Fulton School Of Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: bertan@asu.edu). P. Fontaine, A. N. Mohieldin, S. Peng, S. J. Fang, and F. Dulger are with the Wireless Analog Technology Center, Texas Instruments Incorporated, Dallas, TX 75243 USA. Digital Object Identifier 10.1109/JSSC.2006.872740 circuits in deep-submicron CMOS process is discussed. The RF front-end and baseband circuits are implemented in a 90-nm single poly, six level metal, standard digital CMOS process with a gate oxide thickness of . GSM and CDMA2K signal paths require minimum baseband amplification and filtering stages, utilizing a low-noise continuous-time analog-to-digital converter (ADC) for digital filtering based blocker rejection. The paper is organized as follows. In Section II, the system-level architecture of the multi-mode receive channel is described. In Section III, CDMA2K and GSM RF front-end designs are presented. In Section IV, the baseband signal chain, including the high dynamic range continuous-time ADC, is described. In Section V, characterization results for individual blocks as well as the complete receive chain are presented. II. ARCHITECTURE Reduced supply voltage, limited filtering, and achievable gain in deep-submicron processes pose considerable challenges in RF and baseband receive channel optimization for fully in- tegrated receivers. A classical receiver architecture employing heterodyne downconversion utilizes an external IF filter, greatly reducing dynamic range requirements of the following base- band stages and improving IP2 and IP3 requirements of the channel. However, due to the need for additional frequency synthesizers, high linearity IF downconversion mixers and complex frequency planning for multi-mode operation make the heterodyne approach less attractive for fully integrated receivers. Another critical parameter to consider in multi-mode receiver design is the transmit power and noise leakage in full-duplex (FDD) operation in CDMA mode [2]. Being close to receive channel frequency, high transmit energy would force higher than 15 dBm IIP2 specification. For CDMA receive paths, the direct-conversion technique offers a high integration level and lower power consumption, especially in RF BiCMOS processes [3]. Wide channel bandwidth associated with CDMA systems enables AC coupling, reducing DC offsets and flicker noise impact on bit error rate (BER). Direct-conversion GSM receivers, which utilize low dynamic range baseband ADCs, face several challenges associated with DC offsets due to LO self-mixing and mismatches (IIP2) as well as high flicker noise in the baseband strip [4], [5]. Earlier direct- conversion GSM designs used BiCMOS processes for reducing flicker noise or utilized AC coupling and active calibration for dynamic and static DC offsets [6]. In this design, multiple low- 0018-9200/$20.00 © 2006 IEEE