JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO.4, DECEMBER, 2007 287 Manuscript received Jul. 3, 2007; revised Nov. 6, 2007. * Department of Physics and Electronics, Hansraj College, University of Delhi, Delhi – 110007, INDIA E-mail: amitsehgal112@yahoo.com ** Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi – 110021, INDIA E-mail: rsgu@bol.net.in Poly-crystalline Silicon Thin Film Transistor: a Two- dimensional Threshold Voltage Analysis using Green's Function Approach Amit Sehgal*, Tina Mangla**, Mridula Gupta**, and R. S. Gupta** Abstract—A two–dimensional treatment of the potential distribution under the depletion approximation is presented for poly–crystalline silicon thin film transistors. Green’s function approach is adopted to solve the two–dimensional Poisson’s equation. The solution for the potential distribution is derived using Neumann’s boundary condition at the silicon–silicon di–oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain– boundaries. Also short–channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model. Index Terms—Poly–silicon TFT, modeling, grain– boundary effects, short channel effects, drain– induced barrier lowering I. INTRODUCTION Recently polycrystalline silicon (poly–Si) thin–film transistors (TFTs) have emerged as the device of choice for many applications with desirable electrical characteristics. These include, the integrating driver circuits and pixel transistors on the same glass panel, active matrix liquid crystal displays (AMLCDs) in notebook computers and high definition televisions (HDTVs), printer heads, scanners, synchronous random access memories (SRAMs), image sensors, high performance electrically erasable programmable read only memories (EEPROMs), three–dimensional large scale integrated (LSI) circuits and system–on–panel applications [1–5]. Also, a high–resolution active– matrix microencapsulated electrophoretic display (EDP) driven by polycrystalline–silicon thin–film transistors (poly–Si TFTs) with integrated drivers have been developed [6]. However, the conventional poly–Si TFTs have poor field effect mobility and high leakage current due to the grain–boundaries in the channel region [7–8]. The random distribution of grain sizes and grain– boundary locations lead to unacceptable degradation of device performance for very large scale integrated (VLSI) applications [9]. As the dimensions of poly–Si TFTs are reduced to sub–micrometer scale [10], a decrease in the number of grain–boundaries occurs and this leads to many favorable characteristics such as higher mobility, steeper sub–threshold slope, lower threshold voltage and lower leakage current. A successful design of circuits using poly–Si TFTs requires a proper understanding of its electrical properties. Several models (physics based, empirical and analytical) have been proposed to predict the characteristics of poly–Si TFTs [11–21] but these do not give insight into the device behavior due to the effects