Communication cost aware huristic approach for application task mapping onto network on chip architectures Alireza Mahini Computer department Islamic Azad University, Gorgan branch Gorgan, Iran Samira katebnavaz razlighi Mirdamad non-profit institution of higher education in Gorgan Gorgan, Iran Abstract—Task mapping problem is an important aspect of network on chip design. The optimal mapping tasks have a direct impact on consumption power, performance and speed of running. The use of mesh topology in the network on chip prevents the complexities of implementation. In this paper, a method has been proposed that uses the two-stages categorizing tasks (to shrink the search space) and mapping tasks in network on chip. When big graphs are selected for mapping on NoC, the obtained results of using our method have the lowest cost in communication. Keywords- Tasks mapping; network on-chip (NoC); mesh topology. I. INTRODUCTION Network on chip is an example of a new design and architectures on chip which aims to overcome the design problems and effectiveness limitations of bus-based system on chip (SoC) methods. Architecture of systems based on network on chip contains tens of hundreds homogeneous core which are connected to each other through an interconnection network. In each node of the network, processing cores are connected to a router and this router is connected to other routers via point to point connections via interconnection network. The most important benefits of network on chip are scalability, reusability, predictability, the ability to optimize power and delay and variation [1]. Because of symmetry and simplicity of implementation, mesh topology is used in an integrated circuit and routing algorithm [2, 3]. The main challenge in network on chip is the task assignment on processing cores. Tasks that are mapped to the cores are associated with other tasks through network bed on chip. As a result, task mapping is the most important issues of network on chip; so that, this has a direct impact on consumption power, speed of implementation, and performance. Definition 1: G(T,E) is a directed graph in which each vertex ti ϵ T represents a task and edge ei,jϵE shows a correlation between two tasks i and j. Weight of edge ei,j is shown by commi,j that is the required bandwidth from the connection of two tasks ti and tj. Definition 2: P(U,F) is a directed graph to show the on- chip network connected graph that the vertex uiϵU is a connective node and directional edge fi,jϵF is a physical link between vertices ui and uj. Mapping the graph G(T,E) on a connected graph P(U,F) is defined by the following function: Map:Tﾆ U (1) So that: ∀ti ϵT ,∃uj ϵU and map(ti)=uj (2) This function is a one to one function that allocates task ti to the router uj. Mapping can be done only when∣T∣≤∣U∣ [4]. A model of energy consumption is provided that it is used to estimate the average energy for transmitting a single bit of data from node Ui to neighboring node Uj. Eui, uj= dui , uj × (ELbit + ESbit)×Nij = dui , uj × Ebit ×Nij = d(map(vi),map(vj)) × e(vi,vj) (3) d(map(vi),map(vj)): Manhattan distance map(vi) and map(vj) ESbit: Consumed energy in switch for switching process of one bit ELbit: Consumed energy for bit transfer from a link between two hops. Vi,j: The number of transferred bits from i to j e(vi,vj): Power consumption for transmission of data between tile vi and tile vj. If there is not any communication data between tile vi and tile vj, E(vi,vj)=0. Ebit = ESbit + Elbit (4) According to the above analysis, the total consumption power from data transfer can be written as follows: E(C) = d(map(vi),map(vj)) × E(vi,vj) (5) The aim of optimizing energy consumption in data transmission leads to find a map from TG(V,E) to PG(U,F) with at least E(c) [5]. International Journal of Computer Science and Information Security (IJCSIS), Vol. 14, No. 8, August 2016 287 https://sites.google.com/site/ijcsis/ ISSN 1947-5500