104 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 8, NO. 3, SEPTEMBER 1998 Monte Carlo Optimization of Superconducting Complementary Output Switching Logic Circuits Mark Jeffery, Member, IEEE, Willem J. Perold, Member, IEEE, Zuoqin Wang, and Theodore Van Duzer, Fellow, IEEE Abstract— The authors have previously proposed a new su- perconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been de- signed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5–10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5–10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix. Index Terms— Monte Carlo methods, superconducting device testing, superconducting integrated circuits, yield optimization. I. INTRODUCTION P RACTICAL applications of superconducting logic will require digital circuits that can operate at 10-Gb/s clock speeds and beyond. Unfortunately, Josephson circuits are espe- cially sensitive to process variations and, in the case of voltage- state logic, increasing clock speeds beyond 2 Gb/s tends to seriously degrade circuit margins [1]. We have proposed a new type of voltage-state logic called complementary output switching logic (COSL) [2], [3]. These circuits were optimized for 5–10-Gb/s operation using a Monte Carlo method so that they are relatively robust to process variations. In the present work the Monte Carlo optimization method is described in detail and is applied to 2- and 3-bit encoder circuits for a flash analog-to-digital converter (ADC). A number of factors combine to make reaching the goal of 10-Gb/s superconducting circuits challenging. At a funda- mental level the primary roadblocks have been flux trapping and process variations. Trapped flux in or near Josephson junctions significantly depresses junction critical currents and can, by reducing the overall circuit margins, prevent large Manuscript received November 14, 1997; revised March 20, 1998. This work was supported by University Research Initiative under Grant ONR N00014-92-J-1835. M. Jeffery, Z. Wang, and T. Van Duzer are with the Department of Electrical Engineering and Computer Sciences, The University of California, Berkeley, CA 94720-1770 USA. W. J. Perold is with the Department of Electrical and Electronic Engineer- ing, University of Stellenbosch, Stellenbosch 7600, South Africa. Publisher Item Identifier S 1051-8223(98)06853-5. circuits from operating. We have previously studied the flux trapping problem in detail and demonstrated that with good shielding and moats one can practically eliminate flux trapping in the Josephson circuits [4]. Process variations can also significantly reduce circuit margins and can prevent large digital circuits from operating correctly [5], [6]. We have, therefore, developed a circuit optimization method which explicitly includes process variations. We combine experimental measurements on process spreads with Monte Carlo simulations. The COSL gates are optimized using a Monte Carlo method, and we iterate between basic gates and complex circuits to optimize the yield of large circuits. Simulation examples are given for 2- and 3-bit encoder circuits, and experimental test results for 2-bit encoder circuits operating at 1–4 Gb/s are presented. Design rules for optimal COSL circuit design are also discussed. The simulations demonstrate that COSL circuits should have a significantly higher theoretical yield than modified variable threshold logic (MVTL) circuits [7], [8] in the clock frequency range 5–10 GHz. Note that while we specifically apply Monte Carlo optimization to voltage-state logic, the optimization technique is also applicable to rapid single flux quantum (RSFQ) circuits [9]–[11]. We review the basic COSL gates in the following section. Section III describes experimental testing results to determine local process variations in critical current and resistance, and the basic Monte Carlo optimization method is described. Two examples are given in Section IV: 2-bit and 3-bit en- coders for fully parallel flash ADC’s. The 2-bit encoder is compared to a similar MVTL encoder, and yields from Monte Carlo calculations are given for various process spreads. Design rules, circuit layouts, and experimental test results are described in Section V, and a summary and conclusion are given in Section VI. The HSPICE model used for the simulations is listed in the Appendix. II. REVIEW OF COSL GATES We first briefly review the basic ideas of the COSL family [2], [3]. Fig. 1(a) shows the OR/AND gate, and Fig. 1(b) the NOR/NAND gate. The XOR function is derived from the OR gate by including a 300- A Josephson junction in series with the inputs, Fig. 1(a). All of the gates consist of a one-junction SQUID input stage and a two-junction SQUID output stage [12]. The two-junction SQUID in the output stage is connected in series with a Josephson junction. The COSL circuits are designed to use a three-phase sinusoidal clocking scheme, and the input and output stages of the gates use two of the clock 1051–8223/98$10.00  1998 IEEE