A four transistor rail to rail ultra lowvoltage transconductance amplifier Yngvar Berg and Øivind Næss Department of Informatics, University of Oslo, Blindern, N-0316 Oslo, Norway yngvarb@ifi.uio.no August 25, 1999 Abstract This paper describes a symmetric ultra lowvoltage (ULV) rail-to-rail CMOS am- plifiers using floating gates. Simulation of a compact differential ULV amplifier is presented. 1 Introduction The minimum supply voltage in low-voltage circuits [1] can be defined as V sup,min = 2(V gs + V sat ). The low-voltage circuits are able to operate on a supply voltage of two stacked gate-source voltages and two saturation voltages. Differential amplifiers are biased with a transistor feeding a differential pair. The current level is set by the bias transistor, and the minimum input voltage in a NMOS input pair is given by V bias + nV dsat <V in <V dd , where n is the slope factor modeling the body effect. The bias voltage is proportional to the threshold voltage for a given bias current. To provide a cut-off in the MHz range the bias transistor can not be operated in deep weak inversion, hence the input voltage and supply voltage are limited by the threshold voltage and the saturation voltage and the body effect (V in min ,V dd > 1V ). By eliminating the bias transistor we can decrease the supply voltage further (to n4U T ≈ 200mV ). The challenge is to design a differential input stage without the traditional dif- ferentail pair. Current mode analog circuits using the floating-gate transistor [2] and the floating-gate approach can be exploited to design ultra lowvoltage analog and digital circuits [3, 4, 5]. In this paper we exploit the multiple input FGUVMOS transistor to design a ultra lowvoltage rail-to-rail symmetric amplifier. In section 1 the FGUVMOS transistor is shortly described and in section 2 floating-gate analog inverters are presented. The double input floating-gate inverter is presented in section 4 and a symmetric differential ULV amplifier is described in section 5. 2 FGUVMOS circuits A change in the stored charge of the floating gate will effectively shift the threshold voltage seen from the capacitively coupled input terminal. The success of this approach is clearly 1