1288 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 6, JUNE 2007 Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation Runsheng Wang, Student Member, IEEE, Jing Zhuge, Student Member, IEEE, Ru Huang, Senior Member, IEEE, Yu Tian, Han Xiao, Liangliang Zhang, Chen Li, Student Member, IEEE, Xing Zhang, Member,IEEE, and Yangyuan Wang, Fellow,IEEE Abstract—In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time. Analog/RF figures of merit of SNWTs are studied, including transconductance efficiency g m /I d , intrinsic gain g m /g d , cutoff frequency f t , and maximum oscillation frequency f max . The results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog/RF applications. The impact of nanowire cross-sectional shape fluctuation that is caused by process varia- tion is studied and found to be relatively severe, and the acceptable variation tolerance for RF integrated circuit design is given. Index Terms—Analog, process variation, radio frequency (RF), Si nanowire transistor (SNWT). I. INTRODUCTION A S DOWNSCALING of MOSFETs approaches the end of the International Technology Roadmap for Semiconduc- tors (ITRS) [1], the Silicon nanowire transistor (SNWT) [2]–[5] with multigate or gate-all-around architecture is attractive as one of the promising candidates for future CMOS technology, due to its short-channel-effect immunity, suppressed floating- body effects, improved transport property [6], and CMOS compatibility [3]–[5]. So far, most of the investigations that are performed on SNWTs have focused on their dc characteristics and fabrication [3]–[10], while their potentials in RF applications have not been reported. In addition, intrinsic parameter fluctuations, which are caused by process variation in such small MOSFETs, have emerged as a major scaling limitation for nanodevices. The analog/RF figures of merit (FoMs) and the impact of process variations on the RF performance of SNWTs are investigated in this paper for the first time. In the following part of this paper, the device structure and simulation approach are described. Then, simulation results are discussed, including the analog/RF performance and the influence of nanowire cross-sectional shape variations. Finally, conclusions are given. Manuscript received October 25, 2006; revised March 22, 2007. This work was supported in part by the National Natural Science Foundation of China under Grant 60625403, Special Funds for Major State Basic Research (973) Projects, and the NCET Program. The review of this paper was arranged by Editor M. Reed. The authors are with the Institute of Microelectronics, Peking University, Beijing 100871, China (e-mail: ruhuang@pku.edu.cn). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2007.896598 Fig. 1. (a) Schematic view of the SNWT device structure. (b) Simulated transfer characteristics of a 10-nm gate-length SNWT with a diameter of 3 nm in this paper, compared to the result in [7]. II. DEVICE STRUCTURE AND SIMULATION A computationally experimental structure is shown in Fig. 1(a). The simulated SNWT has a diameter t si in the range of 3–10 nm, an oxide thickness of 1 nm, a source/drain (S/D) region that is doped at 2 × 10 20 cm -3 , and an intrinsic channel (1 × 10 15 cm -3 ). Gate length L g is 10 nm, and there is no gate- to-S/D overlap. Supply voltage V dd is chosen as 0.4 V for low- power design consideration. A carefully calibrated 3-D density-gradient quantum correc- tion drift-diffusion model [11]–[18] is adopted in this paper using Synopsys TCAD Sentaurus Device simulation tools [19]. The quantum potential correction (density-gradient quantum model) [11]–[15] is included to simulate dimensional confine- ment effect in thin nanowires. With careful parameter modi- fication, it can reproduce device electrical characteristics that are simulated by full quantum mechanical models or Monte Carlo simulation, which are the most accurate but much costly [16]–[18]. In this paper, the transfer characteristics of cylin- der gate-all-around nanowire MOSFET have been calibrated 0018-9383/$25.00 © 2007 IEEE