1502 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 10, OCTOBER 1998 A 16 16 Nonvolatile Programmable Analog Vector-Matrix Multiplier Amer Aslam-Siddiqi, Student Member, IEEE, Werner Brockherde, Member, IEEE, and Bedrich J. Hosticka, Senior Member, IEEE Abstract—In this paper, we present a 16 16 analog vector- matrix multiplier with analog electrically erasable and pro- grammable read-only memories (EEPROM’s) used as nonvolatile storage for the weight matrix values. Each weight matrix value is stored in an EEPROM transistor as a change of the threshold voltage, and the same EEPROM transistor is used for the multiplication by utilizing the square-law characteristic of the metal–oxide–semiconductor field-effect transistor. This allows a very simple circuit for the multiplier array with a size of about 1 1 mm . The vector-matrix multiplier has been fabricated in a 1.5- m single-poly complementary metal–oxide– semiconductor/EEPROM technology and successfully tested. Index Terms— Analog memories, analog multipliers, erasable and programmable read-only memory (EPROM). I. INTRODUCTION T HE vector-matrix multiply operation is defined as sum of products, namely with an input vector a matrix of stored weight values and the output vector This general function can be used in various signal-processing algorithms and in a large number of neural-network algorithms. Among the most typical are mul- tiple one-dimensional convolution or correlation operations, which are useful in many applications in image processing. The advantage of an analog implementation of the vector- matrix multiplier in comparison to a digital realization are small chip size and low power consumption. The analog multiplier occupies only a small silicon area, so that an array of multipliers operating in parallel can be realized. For analog in- put and output signals, analog/digital and digital/analog (D/A) conversions can be saved if the multipliers are implemented as analog devices. Fig. 1 shows the schematic of a vector-matrix multiplier that is suitable for an implementation as an analog VLSI circuit, where the values and are assumed to be voltages. The values of the input vector are multiplied in each column by the stored weights and are summed in each horizontal row. The results are the output values , Manuscript received September 29, 1997; revised April 21, 1998. This work was supported by Siemens AG, Munich, Germany, under subcontract within the research program “Electronic Eye” supported by the German Federal Ministry of Education, Science, Research, and Technology, Bonn, Germany. The authors are with the Fraunhofer Institute of Microelectronic Circuits and Systems, Duisburg D-47057 Germany. Publisher Item Identifier S 0018-9200(98)06999-6. Fig. 1. Schematic of a vector-matrix multiplier. which are available in parallel in each row. The analog weight matrix values are stored at each multiplier site so that all multipliers in the array can multiply in parallel without the necessity to fetch the weight from an external memory. An alternative analog storage for the weight values are capacitors [1], [2], but these can store an analog voltage only for a short time. For this reason, the capacitors need a repeated signal refreshing using an additional digital memory, where the weight values are stored. In addition to this, a D/A-converter is required that generates the analog voltage for the capacitors. For a nonvolatile storage of the weight values , analog electrically erasable and programmable read-only memory (EEPROM) devices can be used that do not need refreshing. EEPROM devices normally store digital values [3] and thus require relatively simple programming circuitry. Nevertheless, with a controlled programming of the EEPROM’s, analog values can also be stored in EEPROM-based nonvolatile memory [4], [5]. The analog storage of a weight value in an EEPROM cell drastically reduces the occupied silicon area compared to a digital storage of just one bit for each EEPROM device. Some examples for applications of analog EEPROM’s are represented by neural networks for weight storage [6], [7], trimming in analog circuits, cancellation of the amplifier offset [8], and calibration of image sensors [9]. Fig. 2 shows the cross section and the symbolic view of an EEPROM device with an injector gate in a single- poly CMOS technology. The device consists of a standard metal–oxide–semiconductor field-effect transistor (MOSFET) with a gate that is employed as a floating gate. The floating gate is completely isolated and coupled by two thin oxide capacitors to the control gate and the injector gate. The 0018–9200/98$10.00  1998 IEEE