690 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY2009 Voltage-Island Partitioning and Floorplanning Under Timing Constraints Wan-Ping Lee, Hung-Yi Liu, and Yao-Wen Chang, Member, IEEE Abstract—Power consumption is a crucial concern in nanome- ter chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction. The underlying idea behind MSV is the tradeoff be- tween power saving and performance. In this paper, we present an effective voltage-assignment technique based on dynamic pro- gramming. For circuits without reconvergent fan-outs, an optimal solution for the voltage assignment is guaranteed; for circuits with reconvergent fan-outs, a near-optimal solution is obtained. We then generate a level shifter for each net that connects two blocks in different voltage domains and perform power-network-aware floorplanning for the MSV design. Experimental results show that our floorplanner is very effective in optimizing power consumption under timing constraints. Index Terms—Floorplanning, layout, low power, multiple sup- ply voltage (MSV), physical design. I. I NTRODUCTION A S THE CMOS technology enters the nanometer era, power dissipation is a key challenge in nanometer chip design. Power consumption generally breaks down into two sources, dynamic and static power. While static power in mod- ern technology mainly comes from leakage current, dynamic power P switch is incurred from a device’s switching activities. It can be computed by P switch = k · C load · V 2 dd · f (1) where k is the switching rate, C load is the load capacitance, V dd is the supply voltage, and f is the clock frequency. Compared Manuscript received May 30, 2008; revised September 15, 2008 and December 6, 2008. Current version published April 22, 2009. This work was supported in part by Etron, by SpringSoft, by TSMC, and by the NSC of Taiwan under Grants NSC 96-2628-E-002-248-MY3, NSC 96-2628-E-002- 249-MY3, NSC 96-2221-E-002-245, and NSC 96-2752-E-002-008-PAE. An earlier version of this paper was presented at the 2006 and 2007 IEEE/ACM International Conference on Computer-Aided Design in November 2006 and 2007 [12], [13]. This paper was recommended by Associate Editor I. Markov. W.-P. Lee is with the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan, and also with the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213 USA (e-mail: planet@eda.ee.ntu.edu.tw). H.-Y. Liu is with the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan, and also with Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu 300, Taiwan (e-mail: dianel@eda. ee.ntu.edu.tw). Y.-W. Chang is with the Department of Electrical Engineering and the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan (e-mail: ywchang@cc.ee.ntu.edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCAD.2009.2013997 with static power, dynamic power often dominates the total power consumption in high-frequency circuit design. In a VLSI design, power consumption and performance optimizations often conflict with each other. Minimizing power consumption and simultaneously satisfying the performance constraint is a challenging problem. Researchers have proposed many low-supply-voltage approaches, among which multiple supply voltage (MSV) [23] is a popular technique for power consumption reduction. The underlying idea behind MSV is the tradeoff between the power saving and performance. Under the performance constraints, it is desired to assign cells along noncritical paths with lower power supply voltages for power saving. Thus, the timing slack available on noncritical paths can be effectively converted to power saving. There are two major categories of existing algorithms for the VDD assignment, clustered voltage scaling (CVS) [23] and ex- tended CVS (ECVS) [24]. Both algorithms assign appropriate supply voltages to gates by traversing a combinational circuit from the primary outputs (POs) to the primary inputs (PIs) in a levelized order. CVS dose not allow low VDD (VDDL) gates to drive high VDD (VDDH) gates. Relaxing this restriction, ECVS uses level shifters for VDDL gates to drive VDDH ones. As a result, ECVS can provide an appreciably larger power re- duction compared with CVS. For example, Kulkarni et al. [18] recently presented a heuristic based on ECVS for power saving. In addition to CVS and ECVS, Chang and Pedram [7], [8] applied dynamic programming for voltage assignment. In phys- ical design, Wu et al. [26] minimized the number of voltage islands after placement. (Each voltage island is composed of cells/blocks with the same supply voltage.) They focused on the minimization of the number of voltage islands but did not consider the constraint imposed by the architecture of the power/ground (P/G) network. To generate a good physical topology for MSV, Ma and Young [20] partitioned voltage islands and assigned voltage levels during floorplanning. In Ma and Young’s work, the voltage-level choices are independent of timing effects; any voltage-level choice can satisfy the timing constraint. In other words, there is no tradeoff between power saving and performance. Although MSV techniques have been studied extensively, there are some deficiencies in the previous works. 1) None of those previous works considers the physical positions of level shifters, which is essential for voltage conversion between two circuit components operated at different supply voltages [21]. An inferior level-shifter placement may worsen the timing, and thereby, the timing constraint might be violated. 0278-0070/$25.00 © 2009 IEEE Authorized licensed use limited to: National Taiwan University. Downloaded on May 30, 2009 at 10:39 from IEEE Xplore. Restrictions apply.