Hardware implementation of the Encoder Modified Mid-band exchange coefficient technique (MMBEC) based on FPGA Mohamed E. Elhadedy, Ahmed H. Madian, Hassan I. Saleh, Mahmoud A. Ashour Radiation Engineering Department, NCRRT, Egyptian Atomic Energy Authority, Cairo, Egypt. Mohy A. Aboelsaud Faculty of Engineering, Mansoura University Mansoura,Egypt Abstract- In this paper, the modified mid-band exchange coefficient (MMBEC) image watermark technique has been realized on FPGA platform. This technique is implemented on xilinx XCV800 –pq240 chip and Lab-view software as graphical user interface. The MMBEC technique utilizes 49% of the chip area and operating maximum frequency of 36 MHz. A performance comparison between the software and hardware implementations has been discussed. It declared that the hardware implementation improves the execution time 7 times faster than the software. I. INTRODUCTION Digital watermarking has become an integral part of multimedia because the internet has increased the amount and ease of public access to copyrighted materials. Protected materials can be downloaded or obtained by other methods and used without the consent of the copyright holder [1,2,3,4]. Digital watermarking allows ownership of the copyright to be established. Two basic styles of watermarking are used. Visible watermarking embeds an image such as a company logo into the image to be protected. The watermark is meant to be seen by anyone viewing the image, but in such a way that it does not interfere too drastically with the image itself. Additional discussion of visible watermarking can be found in [5,6,7]. Invisible watermarking embeds an image into another so that the viewer is unable to see the watermark [8,9]. The aim of this paper is presented the hardware design and implementation of insertion operation in MMBEC technique based on FPGA. II. Hardware Design of Watermark Insertion in MMBEC Technique Modified mid-band exchange coefficient technique MMBEC technique [10, 11] is an improvement of the classical MBEC technique [12] which is used to embed watermark in host image. Fig.1 shows the complete architecture for the entire watermark insertion in MMBEC technique, which includes four main hardware operative parts, which implement the 2D-DCT calculation, Inserter, Adjuster and 2D-IDCT calculation [11]. Fig.1. Architecture of Watermark Insertion in MMBEC Technique The first part 2D-DCT block contains two operative parts, which implement the 1-D DCT calculation (The modified Loeffler’s technique [11, 13]), transpose memory that transpose data between the two passes of 1-D DCT as shown in Fig.2 and Fig.3. Data transfer between the operative parts done by using pipeline fundamental as shown in Fig.4. The second part, inserter block is to embed the watermark object into the host image after calculating the 2-D DCT confidents without making any distortion on the host image. The mechanism of the inserter block includes two arrays of registers, two Multiplexers 2 x 1, swap generator component as shown in Fig.5., AND gate, NAND gate and a 3 bits counter. 978-1-4244-1847-3/07/$25.00 ©2007 IEEE IEEE ICM - December 2007