Low Area FSM-Based Memory BIST for Synchronous SRAM Nur Qamarina Mohd Noor, Yusrina Yusof, Azilah Saparon Department of Electronic, Faculty of Electrical Engineering, Universiti Teknologi MARA, 40000, SHAH ALAM, MALAYSIA Abstract- As the memory enters submicron technology, new test algorithm that will be able to give a better fault coverage such as to detect all intra-word coupling fault (CF) has been widely developed. In order to implement this algorithm to the memory, test technique such as BIST is utilized. Common types of memory built-in-self test (MBIST); microcode-based MBIST and FSM-based MBIST. The popular approach of designing various kind of MBIST architectures are either by targeting to reach specific testing requirement such as on full speed and at speed or by considering the cost-constraint and area overhead such low-cost or low-area design. In this paper, FSM-based BIST is designed to be able detecting all intra-word coupling fault (CF) in a synchronous SRAM under low- area constraint of test requirement. I. INTRODUCTION Several MARCH test algorithms [1] are developed to detect intra-word coupling fault in word oriented memories (WOM). As high-volume production and a very low defect- per-million (DPM) level is taking into consideration, new systematic technique of generating data background sequences (DBS) for single cell fault and inter-word CF and DBS for each intra-word fault and the development of the new DBS (MARCH SAM) [2] that will be able to test all types of intra- word faults is introduced. The above test algorithms must be implemented for memories testing by using certain test techniques. One of the popular test techniques is built-in self-test (BIST). A memory BIST (MBIST) consists of a controller to control the flow of test sequences and other components to generate the necessary test control and data. It could be programmable or non- programmable and also could be designed as Finite State Machine (FSM)-based or microcode-based controller [3]-[8]. In FSM-based memory BIST controller, counters are the key component especially in FSM-based memory BIST controller but some FSM-based BIST controller [3] excluded counter from its design. Usually different counters [4], [6] are used to generate the address, test data and read/write sequences. FSMs used in the BIST controller in [4] are run sequentially one after another while in [6], the flexibility of applying different test algorithm in FSM-based BIST controller is introduced. Two types of FSM-based BIST controller architectures are proposed in [5]. Both are designed by using a counter for the test pattern generator and test controller but one is using MISR which is a part of the BIST controller block for output response analyzer (ORA) while another one is using comparator which acts as an external block in the BIST system for ORA. However, designing by using multiple counters and by not including ORA in the BIST controller such as in [4]-[6] would certainly increase the area overhead. Thus, in this paper, a BIST controller circuit that operates on one counter and combined ORA must is proposed to reduce area while maintaining acceptable speed. This paper is organized as follows. In the next section, the proposed MBIST architecture is introduced. The experimental results are discussed in the Section 3 while Section 4 concludes the paper. II. PROPOSED BIST ARCHITECTURE Based on [3]–[6], the design of FSM-based MBIST using MARCH SAM for WOM is developed. The characteristics of the design are as following a. Application of unicounter to run loop of the address generator, data generator and read/write sequences. b. Implementation of nested loop FSMs where all FSMs run concurrently. c. Immediate analysis of output by comparing it right after each BIST sequence and the pass/fail flag is up based on the output. d. Flexibility in changing test pattern because it is stored in read-only memories (ROM). Fig. 1 shows the block diagram of the proposed design. The design consists of SRAM test controller block, SRAM behavioral block and ROMs. 409 2009 5th International Colloquium on Signal Processing & Its Applications (CSPA) 978-1-4244-4152-5/09/$25.00 ©2009 IEEE