Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially- Depleted SOI CMOS Using BSIMPD Pin Su, Samuel K. H. Fung*, Weidong Liu and Chenming Hu Department of EECS, University of California at Berkeley, CA 94720, USA *IBM SRDC, Hopewell Junction, NY 12533, USA pinsu@eecs.berkeley.edu Abstract In this work, we investigate and analyze the impact of gate tunneling on dynamic behaviors of partially depleted SOI CMOS with the aid of the physically accurate BSIMPD model. We examine in particular the impact of gate tunneling on the history dependence of inverter delays. The examination reveals key requirements for capturing the history effect in SPICE modeling. This study suggests that gate tunneling has a strong impact on the delay range and should be considered in SOI circuit simulation. It is crucial for circuit designers to understand and contain the hysteretic delay variations caused by gate current. An accurate SPICE model that includes the oxide tunneling mechanism should be used to quantify the effect without undermining the performance benefit of a partially depleted SOI technology. BSIMPD is one model that attempts to bridge the gap between advanced SOI technologies and circuit design. With its built-in floating-body, self-heating and body-contact modules, BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI chips. BSIMPD has been implemented in Berkeley SPICE3f4 and other commercial SPICE simulators. It may also be the basis for computing the look-up tables used for higher-level timing simulation. 1. Introduction Scaling for high performance has set the stage for partially depleted (PD) SOI to become an important CMOS technology [1, 2]. PD SOI provides a performance gain of 20 to 35 percent over bulk CMOS [1] due to the reduction of junction capacitance and the absence of the body-bias effect in series connected devices, e.g. in NAND and NOR gates. With the same performance (constant delay), SOI can operate at a lower voltage and therefore emerges as a strong contender for low power applications as well. The main barrier to the acceptance of PD SOI by circuit designers, however, is the requirement of careful analysis for the impact of floating body effects on individual blocks [3, 4, 5, 6]. Due to the self-biasing of the floating body, PD SOI circuits present idiosyncratic dynamic behaviors (e.g., history and frequency dependence of switching speed) that may increase the risk of inadequate circuit designs. With oxide scaling, the tunneling current [7, 8, 9] between the gate and the body introduces an element of complication to the history effect. BSIMPD (Berkeley Short-Channel IGFET Model - Partial Depletion) [10, 11] is one SPICE model that attempts to fill the gap. With its built-in floating-body, self-heating and body-contact modules [10, 12], BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI circuits. The accuracy and robustness of BSIMPD have been verified and tested extensively in industry [13, 14, 15]. Since BSIMPD is physically accurate, we may further utilize it as a tool to study the impact of gate tunneling on SOI CMOS so that circuit designers may gain insight to fully exploit the performance leverage offered by SOI. In this paper we investigate the dynamic behavior of a static CMOS inverter, the basic building block of higher order logic circuits, with the aid of BSIMPD. Through a comparison of the circuit behavior, with and without gate current, we examine the impact of oxide tunneling current on dynamic behaviors of PD SOI CMOS circuits. 2. Tunneling Mechanism The origin of SOI dynamic behaviors is the history dependence [16, 17, 18] of the floating body potential. Since the time constant of body charging is different for capacitive coupling, thermal generation and recombination, gate-induced-drain-leakage (GIDL), impact ionization [19], and oxide tunneling, the circuit representation of the floating body in Figure 1 is used in BSIMPD to capture the dynamic behavior of SOI. Among all the body currents, the oxide tunneling, I gb , is playing an increasingly crucial role as the oxide thickness is scaled down (below 25Å) [20]. Figure 2 shows the dominant tunneling mechanism (direct valence-band electron tunneling) responsible for the Proceedings of the International Symposium on Quality Electronic Design (ISQED02) 0-7695-1561-4/02 $17.00 ' 2002 IEEE