HARDWARE SYNTHESIS FROM PROTOCOL SPECIFICATIONS IN LOTOS Keiichi Yasumoto , Akira Kitajima , Teruo Higashino , and KenichiTaniguchi Dept. of Information Processing and Management, Shiga Univ., Hikone, Shiga 522-8522, JAPAN yasumoto@biwako.shiga-u.ac.jp Dept. of Information and Computer Sciences, Osaka Univ., Toyonaka, Osaka 560-8531, JAPAN (kitajima,higashino,taniguchi)@ics.es.osaka-u.ac.jp Abstract: In this paper, we propose a technique for hardware implementation of protocol speci- fications in LOTOS. For the purpose, we define a new model called synchronous EFSMs consisting of concurrent EFSMs and a finite set of multi-rendezvous indications among their subsets, and propose a conversion algorithm from a subset of LOTOS. The de- rived synchronous EFSMs can be easily implemented as a synchronous sequential circuit where all the modules corresponding to the EFSMs work synchronously with the same clock. By applying our technique to the Abracadabra protocol, it is confirmed that the derived circuit handles multi-rendezvous efficiently. 1 INTRODUCTION Due to the growth of computer networks, efficient implementation of communication protocols has been needed. Thus, the techniques for implementing protocols as hard- ware circuits have been stressed in recent years. To specify hardware circuits formally, the description techniques LOTOS [1, 12], Estelle [15] and SDL [13] have been proposed. With these techniques, we can eas- ily describe schemes for hardware circuits using predefined component libraries, and can verify/validate them. However for rapid prototyping, synthesis techniques from the specifications are desirable. Several ideas for hardware synthesis from formal specifications have been proposed [6]. For example, [15] has proposed a synthe- sis technique from Estelle. However, the technique does not deal with the highly structured specifications containing synchronization among concurrent modules like multi-rendezvous. In [7], although a technique to convert timed LOTOS specifica-