An Energy Efficient Fully Integrated OOK Transceiver SoC for Wireless Body Area Networks Bo Zhao * , Yinan Sun * , Wei Zou * , Yong Lian + , Yongpan Liu * , and Huazhong Yang * * Department of Electronic Engineering, Tsinghua National Laboratory for Information Science and Technology Tsinghua University, Beijing, 100084, China. Email: {zhao bo, yanghz}@tsinghua.edu.cn + Department of Electrical Engineering and Computer Science, York University. Email: plian@yorku.ca Abstract—This work presents a low-power high-speed system- on-chip (SoC) for wireless body area networks (WBANs). The SoC is fully integrated with a 10 Mb/s on-off keying (OOK) RF transceiver, digital processing units, an 8051 micro-controlled unit (MCU), a successive approximation (SAR) ADC, and etc. The receiver adopts envelop detector (ED) based structure to improve the energy efficiency. Conventional ED based structure has a poor sensitivity when reaching a bit rate of Mb/s level. To resolve the problem, we design a receiving (Rx) front-end with 77 dB gain at 10 Mb/s data rate, and propose a novel supply isolation scheme to avoid the instability induced by such a high gain. The transmitter is based on a 2 GHz digitally controlled oscillator (DCO), which uses bond wires as inductors to further reduce the power at transmitting (Tx) mode. The digital baseband is designed by a near-threshold design (NTD) method for low power consumption. The chip is implemented with 0.13 μm CMOS technology, measured results show that the receiver consumes 0.214 nJ/bit at -65 dBm sensitivity, and the Tx energy efficiency is 0.285 nJ/bit at an output power of -5.4 dBm. In addition, the digital baseband consumes 34.8 pJ/bit with its supply voltage lowered to 0.55 V, indicating its energy per bit is reduced to nearly 1/4 of the super-threshold operation. I. I NTRODUCTION Wireless body area network (WBAN) will play an important role in future healthcare. Several types of applications require high data rate such as retina implants, capsule endoscopy, and neural recording systems. For such applications, wireless transceiver consumes significant power. Thus, it is crucial to improve power efficiency of wireless transceiver in WBAN applications. Considering the short communication distance used in WBAN, simple modulation schemes such as binary frequency shift keying (BFSK), binary phase shift keying (BPSK), and on-off keying (OOK) are widely adopted [1]– [4]. Among different modulation schemes, OOK transceiver has shown a high data rate at Mb/s level by using sim- ple modulation-demodulation circuits. For example, OOK transceiver with down-conversion receiving (Rx) front-end was reported in [1] which attained a data rate of 2 Mb/s. However, down conversion usually needs power-hungry modules, such as high-performance mixers and a frequency synthesizer. This was evidenced by the energy efficiency of 1.7 nJ/bit at Rx and 1.55 nJ/bit at transmitting (Tx) in [1]. Envelope detector (ED) based OOK receiver has shown a better Rx energy efficiency, e.g. 0.5 nJ/bit in [2] and 0.295 nJ/bit in [3], respectively. However, ED based approach usually leads to poor Rx sensitivities, e.g. -37 dBm in [2] and -45 dBm in [3], which result in a limited communication distance. In addition, data rates in those designs [1]–[3] are limited to less than 2 Mb/s, which is not adequate for some WBAN applications such as endoscope capsule and neural recording system. A 5 Mb/s super-regenerative OOK transceiver was reported in [4], which boosted energy efficiency to 0.363 nJ/bit. The high efficiency, however, was at the cost of several off-chip components. This increases the device size, which is not favored in implants. In this work, we implemented a fully integrated OOK transceiver system-on-chip (SoC) in 0.13 μm CMOS tech- nology. To improve the sensitivity of conventional ED based receivers as well as power efficiency, we boost the gain of Rx front-end by a single-end inverter-based design while keeping power in check. The high-gain induced instability is addressed by a low-power supply isolation scheme. For the transmitter, a bond-wire digitally controlled oscillator (DCO) is implement- ed for low-power carrier generation. For the digital baseband, we lowered its power consumption by near-threshold design (NTD) technique. Therefore, the energy efficiency of the SoC is significantly improved. Fig. 1. System architecture. II. SYSTEM ARCHITECTURE The SoC architecture is shown in Fig. 1, assisted by an antenna, a 1.5 V button battery, a crystal, and bond-wire inductors. There are two main blocks in the SoC, i.e. RF part and digital baseband. The RF transceiver contains an ED based receiver and a DCO based transmitter, whereas a novel low-power supply isolation scheme is proposed for 441 978-1-4799-0280-4/13/$31.00 c 2013 IEEE