IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 3, MARCH 2002 409 Effect of Forward and Reverse Substrate Biasing on Low-Frequency Noise in Silicon PMOSFETs M. Jamal Deen, Senior Member, IEEE, and Ognian Marinov Abstract—The forward body biasing improves the low-fre- quency noise performance of p-channel metal-oxide semicon- ductor (PMOS) transistors by about 8 dB/V. Therefore, for analog design, forward body biasing may be preferred if noise is a concern. This is in agreement with the improvement of other MOSFET parameters such as the decrease of the threshold voltage ( ) or the increase of unity current-gain frequency ( ) on forward substrate- (or body)-source biasing ( ). Also, forward is very attractive for low voltage supply ( V) and low-power, low-noise circuits. A detailed analysis of the dependence of the noise level on and on the gate-source ( ) biasing showed that the dependence on seems to be smaller in weak inversion, and it increases in strong inversion. The dependence on has a turning point at V, independent of body bias, which it seems is due to the activation of oxide traps, as the noise waveform showed a random telegraph signal (RTS) component at V. Generally, it is confirmed that the spectral density of the total low-frequency noise of the drain current is proportional to the square of , i.e., , but it cannot be clearly ascribed to either number fluctuation or mobility fluctuation models. In addition, both models cannot accurately describe the dependence of the noise level on the body bias. Index Terms— noise in MOSFETs, body-bias effects, flicker noise in MOSFETs, low-frequency noise, noise in MOSFETs, noise modeling, substrate-bias effects. I. INTRODUCTION T HE substrate- (or body)-to-source ( ) biasing of MOSFETs can be used as a very effective fine-control of the device’s electrical characteristics. Forward biasing the substrate is attractive for low voltage CMOS applications, because it reduces the threshold voltage ( ) of the MOSFET [1], [2] and speeds-up the device, increasing the unity cur- rent-gain frequency ( ) in analog, and the switching speed in digital CMOS circuits [3]. Reverse body biasing is attractive for low current CMOS applications since the device’s current decrease to the nA range even in the active mode of operation [1]. As MOS device sizes and signal levels are aggressively scaled down, the low-frequency noise (LFN) properties become increasingly important. This is because the signals are no longer significantly higher than the LFN, especially since the Manuscript received April 17, 2001; revised August 27, 2001. This work was supported in part by the Natural Sciences and Engineering Research Council (NSERC) of Canada, Mitel, Ottawa, ON, Canada, and Micronet. The review of this paper was arranged by Editor C.-Y. Lu. M. J. Deen is with the Electrical and Computer Engineering Department, McMaster University, Hamilton, ON L8S 4K1, Canada (e-mail: jamal@mc- master.ca). O. Marinov is with the Technical University-Sofia-FETT, Sofia 1797, Bul- garia (e-mail: omarinov@yahoo.com). Publisher Item Identifier S 0018-9383(02)01559-9. LFN level increases significantly as the device’s size is scaled down [4]–[7]. The aforementioned reasons have motivated our investiga- tion of the low-frequency noise in PMOS transistors from a 0.18 m CMOS technology under low voltage mode of oper- ation, from weak to strong inversion, emphasizing the depen- dence of the LFN on the biasing. For these investigations, we have chosen PMOS transistors from a CMOS-on-P-wafer technology because the n-well (body of the PMOS transistor) can be connected to a potential different from the positive node of the circuit supply voltage, while wafer serves as the common body of the NMOS transistors. Also, if the body-biasing can be used to effectively decrease the low-frequency noise, then this might be an attractive option for analog IC designers. This paper discusses experimental results and it is a signifi- cant expansion of [18]. In Section II, the details of the exper- iments are provided, and the results for the dependence of the total LFN on the gate and substrate biases are presented. Then, number and mobility fluctuations as origin of the noise in PMOSFET are discussed in Section III. Finally, the important results from this study are summarized in Section IV. For con- venience, all voltages are shown in absolute values in this paper. II. EXPERIMENTAL DETAILS AND RESULTS PMOSFETs of dimension 3 m 3 m were chosen to avoid short-channel or periphery effects. In addition, the gener- ation-recombination (GR) noise strongly prevails over the noise in devices with channel areas smaller than 3 m , limiting the low noise applications of PMOSFETs. From detailed DC characterization, it was found that the drain current nA is the border between weak and strong inversion modes of the transistor’s operation. This is because the saturation drain cur- rent is an exponential function of at nA, as shown in Fig. 1, where the DC bias points of the noise measurements are presented. The DC characteristics of the PMOSFET were modeled by using the Tsividis’ model (see [8, p. 427]), which is valid for the saturation mode of operation of MOSFET, since in our noise measurements. From the re- sults of this modeling, we obtained the transconductance of the PMOSFET at every bias point of the noise measurement, as shown in Fig. 2. The LFN measurements were done at bias points of the gate-to-source voltage ( ) from 0.1 V to 1 V,in steps of 0.1 V, and substrate- (or body)-to-source voltage ( ) from 0.6 V (reverse) to 0.6 V (forward), in steps of 0.2 V. A current amplifier Ithaco 1212 with transimpedance gain from 10 to 10 monitored the drain current noise spec- tral density (A /Hz), and converted it into a voltage noise 0018–9383/02$17.00 © 2002 IEEE