A Reed-Solomon algorithm for FPGA area optimization in space applications Gabriel Marchesan Almeida * , Eduardo Augusto Bezerra * , Luis Vitório Cargnini Ψ , Rubem Dutra Ribeiro Fagundes Ψ and Daniel Gomes Mesquita † * Embedded Systems Group, PPGCC, Faculdade de Informática, Catholic University (PUCRS) galmeida@inf.pucrs.br, Eduardo.Bezerra@pucrs.br Porto Alegre, RS, Brazil, 90619-900 Ψ Instituto de Pesquisas Científicas e Tecnológicas, IPCT, PPGEE, FENG, PUCRS lvcargnini@ieee.org, rubemdrf@sapienstek.com Porto Alegre, RS, Brazil, 90619-900 † Instituto de Engenharia de Sistemas e Computadores, Instituto Superior Técnico de Lisboa (INESC) Lisboa, Portugal, 1000-029 mesquita@inesc-id.pt Abstract This work describes an algebraic based design strategy targeting area optimization in reconfigurable computer technology (FPGA). Area optimization is a major issue as smaller components allow for better system adaptation, which is an expected feature of reconfigurable systems for space applications. The approach is applied in the design stage of a component for the communications module of an on-board computer system. The chosen component is a Reed-Solomon encoder, which has been implemented using a Hardware Description Language (VHDL) according to CCSDS recommendations, and targeting an FPGA platform. The paper investigates traditional alternatives for the encoder implementation, introduces the algebraic theory behind the proposed approach, describes the design process and discusses the area figures reached by the new design. 1. Introduction An SRAM based Field Programmable Gate Array (FPGA) is an interesting platform for the implementation of evolvable hardware systems. In the field of space applications, commercial off-the-shelf FPGA devices from leading manufacturers [1] have been around for a while. However, these devices are still not in use as the main processing unit of on-board computers in space applications, mainly because of the risks related to the exposure of SRAM technology to radiation. Even though, scientists from space agencies around the world, and also from the Brazilian Space Program, are interested in this technology for several reasons [2][3]: easy adaptation to new mission requirements after launching; allows “hardware” bug fixes after launching; higher processing power; and reduced size. All these features are of great importance for space systems in general, but the idea behind having a hardware system changing on-the-fly in order to adapt to its environment and application requirements, is the main motivation for the research work at PUCRS [4][5][6]. An on-going project at PUCRS, funded by the Brazilian Space Agency, aims the implementation of the communications module for a future satellite mission, targeting reconfigurable computing technology (FPGA). This on-board module is responsible for receiving telecommands (TC) from a ground-station, and for sending out telemetry (TM) data, as shown in Figure 1. It is a vital module for the mission as a whole, as in case of a problem, a TC may not arrive at its destination resulting, for instance, in an engine for attitude control turned on/off at the wrong moment, or the solar panel pointed at the wrong direction. In order to make the reconfigurable computing system as robust as possible, several strategies have been investigated by the research group at PUCRS, and in other institutions as well: design for verification [7][8], design for testability [9][10], fault-tolerance [11][12], among others. All these efforts are justified as having a dependable system is the first step for a successful space mission. Figure 1. TC/TM flow