Hindawi Publishing Corporation International Journal of Reconigurable Computing Volume 2013, Article ID 802436, 24 pages http://dx.doi.org/10.1155/2013/802436 Research Article Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA Emna Amouri, 1 Habib Mehrez, 1 and Zied Marrakchi 2 1 LIP6, Universite Pierre et Marie Curie, 4 Place Jussieu, 75252 Paris, France 2 Flexras Technologies, 153 Boulevard Anatole France, 93200 Saint-Denis, France Correspondence should be addressed to Emna Amouri; amouriemna@yahoo.fr Received 28 June 2013; Revised 11 October 2013; Accepted 16 October 2013 Academic Editor: Nadia Nedjah Copyright © 2013 Emna Amouri et al. his is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. he wave dynamic diferential logic (WDDL) has been identiied as a promising countermeasure to increase the robustness of cryptographic devices against diferential power attacks (DPA). However, to guarantee the efectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. his paper tackles the problem of unbalance of dual-rail signals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. hen, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree- based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a diferential pair routing algorithm that is speciic to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number. 1. Introduction FPGAs are an attractive platform for cryptographic applica- tions due to their low cost compared to full custom ASIC design and their short time to market period. In addition, their reprogrammability allows upgrading easily the crypto- graphic algorithm. However, unprotected hardware imple- mentations are vulnerable to side channel attacks (SCA). It has been shown that diferential power analysis (DPA) attack [1] is very powerful. DPA is capable of revealing the secret key by measuring power consumption leaked by a cryptographic device. During the last years, many countermeasures have been proposed to protect cryptographic devices against SCA. hey fall into two main categories: the masking logic and the hiding logic. he principle of masking logic is to randomize the power consumption by using a random mask and thus decorrelate the intermediate data from the circuit power consumption. his technique was introduced irst at algorithmic level [2] and then at gate level [3]. It has been shown that this technique can be broken by attacks based on probability density function (PDF) [4] or glitches [5]. To overcome glitch problem, masked dual rail precharge logic (MDPL) [6] has been proposed. It merges masking with dual rail dynamic logic. However, MDPL shows a high area overhead [7]. On the other side, the principle of hiding logic consists in consuming the same amount of power consumption regardless of data inputs. his is achieved by using diferential logic (signals are encoded as two complementary wires) and precharging the diferential signals in every clock cycle. It is also called dual rail precharge logic (DPL). Several implementations of secure dual rail cells have been proposed, speciically for ASICs, such as SABL [8], WDDL [9], STTL [10], and MDPL [6]. he wave dynamic dual rail logic (WDDL) technique, developed by Tiri and Verbauwhede [9], is the most popular DPL countermeasure. It is based on a standard cell low, and it is the most suited for FPGA implementation. However, this technique has been proved to prevent DPA, provided the routing of diferential signals is balanced [11]. his task is hard to achieve in FPGA because routing resources are limited and have thus to be properly shared between diferential components of the design.