Modelling and Synthesis of Optimal Adders under Left-to-Right Input Arrival A. Guyot, S.J. Abou-Samra, M. Aberbour*, A. Houelle*, H. Mehrez* & N. Vaucher * Integrated Systems Design Group, TIMA laboratory, 46, Av. Félix Viallet, 38031 Grenoble, France *LIP6 laboratory, Université Pierre et Marie Curie 4, Place Jussieu, 75252 Paris, France e-mail: Alain.Guyot@imag.fr 1. Abstract In this paper parallel adders with minimum delay and minimum complexity under left-to-right sequential input arrival are investigated. The delay is the result time after the arrival of the last input digits which are the least significant ones. An analytical model of the complexity is established and a synthesis algorithm is described. The algorithm is implemented on a powerful multiview layout synthesis tool called GenOptim[1]. This CAD tool outputs a set of different descriptions including: a netlist view, a layout view, a VHDL behaviour view and finally a test view including functional and structural test patterns with a very high fault coverage. 2. Introduction Fast adders has been a research subject for many years. However, most of them assume that all the input digits are ready at the same time. Our concern in this paper is to implement an adder under sequential input arrival condition starting with the most significant digits. When carry- propagation-free iterative algorithms are used for division or square root extraction, the quotient or the root are produced serially, starting from the most significant digits and has to be converted from redundant notation to standard binary notation by mean of such an adder. The addition delay is the time between the arrival of the least significant input digits and the time where all the output bits are ready. The paper is organised as follows: in paragraphs 3, 4 and 5 the general theory of carry anticipation is recalled. In paragraph 6 two adders are propo- sed as examples for the reader to check that the delay is indeed minimum. The theory, modelling and synthesis are developed in paragraphs 7, 8, 9 and 10. In section 11 we present the GenOptim [2,3] implementation methodology. A layout example is finally provided. 3. Carry in addition In an n-bit addition, let us note a i , b i , s i and c i the bits at the i th position (weight 2 i ) of respectively the two addends A and B, the sum S and the carry. At each digit position i, the next carry is either generated (c i+1 = 1), killed (c i+1 = 0) or propa- gated (c i+1 = c i ). These situations are described by three bits g i = a i ∧b i , k i = a i — ∧ b i — and p i = a i ⊕b i . Any two out of the three bits can give the next carry: c i+1 = g i ∨ p i ∧ c i or c i+1 = g i ∨ k i — ∧ c i or c i+1 = k i — ∧ ( p i — ∨ c i ). The first form is sometimes preferred because p i is also useful for s i , and the second because k i — is given by a simple "or" gate. In the rest of the paper, we choose p i and g i . 4. Carry look-ahead adders Let us note now P i j the group propagate and G i j the group generate, with n-1 ≥ j ≥ i ≥ 0 . The bit P i j indicates that the carry propagates from position i up to j, that is c j+1 = c i . The bit G i j indicates that a carry is generated somewhere between positions i and j and propagated from this location up to position j and yields c j+1 = 1.We have P i i = p i , G i i = g i and since there in no carry-in (c 0 = 0), c i+1 = G 0 i . The n bits of the sum S are given by s i = p i ⊕ c i = p i ⊕ G 0 i-1 for i > 0 and s 0 = p 0 . For any k such that j > k ≥ i , the couple of bits ( P i j , G i j ) can be recursively computed from the couples (P k+1 j , G k+1 j ) and (P i k , G i k ) as follows: ( P i j , G i j ) = (P k+1 j ∧ P i k , G k+1 j ∨ P k+1 j ∧ G i k ). Let us note ∆ the operator introduced by Brent and Kung [1] : (P i j , G i j ) = (P k+1 j , G k+1 j ) ∆ (P i k , G i k ). In the figures 1 and 2 the icon for ∆-cells is , each connection carries two bits (P,G). It is easy to check that the operator ∆ is associative and non commutative.