Graphene/SiC/Si FETs with SiCN Gate Stack T. Suemitsu a , M. Kubo a , H. Handa a , R. Takahashi a , H. Fukidome a , M. Suemitsu a,b and T. Otsuji a,b a Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan b CREST, Japan Science and Technology Agency, Tokyo 102-0075, Japan Graphene-on-silicon field-effect transistors (GOSFETs) are studied as a candidate of next generation transistors. Graphene is formed on SiC layers grown on Si substrates. As well as the channel material, the gate stack is also a key component of FETs. In this study, SiCN deposited by plasma-enhanced chemical vapor deposition (PECVD) using hexamethyldisilazane (HMDS) vapor is studied. During PECVD, hydrogen is used as a carrier gas in addition to HMDS vapor. This becomes an advantage in the graphene process because hydrogen has cleaning effect on graphene surface. To verify this effect, SiCN gate stack is applied to the graphene on SiC substrates. FETs with SiCN gate stack exhibit clearer ambipolar characteristics and larger drain current density than FETs with conventional SiN gate stack. The SiCN gate stack is also applied to GOSFETs. Resulting devices also exhibit ambipolar characteristics and larger current density than previously reported GOSFETs with SiN gate stack. Introduction Graphene is becoming a promising candidate of channel materials in field-effect transistors because of its high carrier mobility both for electrons and holes. Currently the current gain cutoff frequency of over 100 GHz is reported for graphene FETs with a gate length of 240 nm [1]. There are some approaches in the graphene synthesis. A thermal decomposition of SiC is one of major approaches to form graphene [2,3]. Usually this approach is possible if one uses SiC substrates. In 2009, M. Suemitsu et al. reported the epitaxial graphene on Si substrates [4,5]. In this approach, a SiC layer is first grown on Si substrates and then the surface of the SiC layer is thermally decomposed to form graphene by annealing at ultrahigh vacuum. The top-gate graphene-on-silicon FETs (GOSFETs) were fabricated using a SiN gate stack [6]. However these devices have issues that the drain current density was very small (in the order of 10 -3 mA/mm) and a deep negative shift in the Dirac voltage (~ -60 V) was observed. In this paper, a SiCN gate stack is studied for graphene FETs. Using the SiCN gate stack, clear ambipolar characteristics with the conduction minimum at zero gate voltage is confirmed by the graphene FETs on SiC substrates. Then this approach applied to GOSFETs. The drain current density increases by two orders of magnitude comparing to the previously reported GOSFETs using the SiN gate stack. ECS Transactions, 41 (6) 249-254 (2011) 10.1149/1.3629973 ©The Electrochemical Society 249 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 54.221.174.100 Downloaded on 2016-10-24 to IP