IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 8, AUGUST 2012 2093 Characterization and Modeling of Hot Carrier-Induced Variability in Subthreshold Region Paolo Magnone, Felice Crupi, Nicole Wils, Hans P. Tuinhout, and Claudio Fiegna Abstract—We developed an analytical model that is able to pre- dict the evolution of the subthreshold slope variability associated with hot carrier (HC) stress. The model assumes that HC stress generates interface states with a Poisson distribution and that the number of HC-induced interface states increases linearly with the HC-induced subthreshold slope variation. We validate the model by means of extensive variability data sets collected on n-channel MOSFETs in 45- and 65-nm CMOS technologies. Furthermore, we investigate the correlation between the threshold voltage and the subthreshold slope fluctuations in order to fully characterize their impact on the subthreshold current variability. Index Terms—Hot carrier, mismatch, MOSFET, subthreshold slope, threshold voltage, variability. I. I NTRODUCTION T HE VARIABILITY in the performance and power con- sumption of CMOS integrated circuits is one of the most critical problems faced by circuit designers due to the aggres- sive scaling of the device dimensions and the associated reduc- tion of the power supply [1]–[8]. On the one hand, MOSFETs have reached the decananometer scale, where individual dopants or defects substantially affect the device performance. On the other hand, aggressive supply voltage scaling to below the device threshold voltage (V T ) is a compelling strategy for ultralow power CMOS logic circuits [9]–[12]. Random device fluctuations in the subthreshold region degrade the circuit per- formance, thus limiting the minimum attainable supply voltage [13]. Recently, we reported a simple model of the subthreshold current mismatch, which takes into account the effect of V T as well as subthreshold slope (S) fluctuations, and their correla- tion [8]. We demonstrated that, in the subthreshold region, the subthreshold slope fluctuations can significantly affect the drain current fluctuations. Several experimental studies have shown that wear-out mechanisms, such as negative-bias temperature Manuscript received January 17, 2012; revised March 21, 2012; accepted May 15, 2012. Date of publication June 18, 2012; date of current version July 19, 2012. This work was supported in part by the ENIAC-120003 MOd- eling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems project. The review of this paper was arranged by Editor H. S. Momose. P. Magnone and C. Fiegna are with the ARCES, University of Bologna, 47521 Cesena, Italy (e-mail: pmagnone@arces.unibo.it; cfiegna@arces. unibo.it). F. Crupi is with the DEIS, University of Calabria, 87036 Rende, Italy (e-mail: crupi@unical.it). N. Wils and H. P. Tuinhout are with the NXP Semiconductors, 5656AE Eindhoven, The Netherlands (e-mail: nicole.wils@nxp.com; hans.tuinhout@ nxp.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2012.2200683 instability (NBTI) and hot carriers (HC), introduce additional variability in the device electrical parameters [14]–[21]. This additional source of variability is ascribed to the stress-induced bulk oxide and interface-trapped charges. Note that the other sources of variability, such as random dopant fluctuation, line edge roughness, and metal gate granularity, do not change during device lifetime. In [21], we investigated the impact of HC stress on the variability of V T and S in 45- and 65-nm CMOS technologies. We proposed a model for the HC-induced V T variability which is able to accurately predict the evolution of the HC-induced V T variability from the knowledge of an empirical parameter and the evolution of the HC-induced V T shift. To complete this picture, in this paper, we describe an analytical model that is able to predict the evolution of the S variability during HC stress, and we validate the model by means of experimental data in 45- and 65-nm CMOS technolo- gies. In addition, we investigate the correlation between the V T and S fluctuations in order to fully characterize their impact on the subthreshold current fluctuations. II. EXPERIMENTS The experimental data were obtained from populations of n-channel MOSFETs processed in 45- and 65-nm foundry CMOS technologies with approximately 1.85-nm SiON gate dielectrics. The channel width (W ) is 1 μm, and the gate lengths (L) were estimated to be 37 nm (45-nm process) and 50 nm (65-nm process). The mismatch analyses were done on pairs of transistors, in order to exclude deterministic parametric wafer gradients from the observed variabilities. HC-induced variability was investi- gated using a conventional cumulative measure–stress–measure approach implemented on a Keithley 4200 SCS parameter ana- lyzer, as reported in Fig. 1. For the 65-nm (45 nm) technology, the HC stresses have been implemented by using a gate voltage V GS equal to 1.2 V (1.1 V) and three different values of the drain voltages V DS equal to 2, 2.2, and 2.4 V (1.7, 1.8, and 1.9 V). For each stress bias, measurements were done after 10, 30, 100, 300, and 1000 s to monitor the evolution of the HC-stress effects. Since the statistical analysis was carried out for populations of 80 nMOSFET pairs for each stress bias, an ensemble of about 1000 transistors has been used for this paper. In this paper, we adopt the following nomenclature: δ denotes a difference between the paired devices, and Δ denotes a stress- induced shift in one device. The S mismatch in the stressed pair can be written as δS STRESS = δS FRESH + δS HC (1) 0018-9383/$31.00 © 2012 IEEE