Signal Integrity Loss in Bus Lines due to Open Shielding Defects Victor Avenda˜ no, Victor Champac INAOE Electronic Department Puebla, Mexico C.P. 72840 vico@inaoep.mx, champac@inaoep.mx Joan Figueras Universitat Polit` ecnica de Catalunya-UPC Electronic Department Barcelona, Spain C.P. 08028 figueras@eel.upc.es Abstract Interconnect structures in high speed circuits play an important role in present CMOS technologies. Inductance and capacitance coupling effects (crosstalk) may cause a significant loss in signal integrity in high performance sys- tems. One way to reduce these effects is to place a signal line between two grounded lines (shield). In this paper we study the influence of defective grounding of shielding lines. We focus on resistive open defects due to manufacturing problems or broken vias. Faulty shields may cause under- shoots or ringings in signal traveling in long interconnect lines. Simple expressions for undershoots and overshoots have been derived using dominant poles and employed to determine the zones of signal integrity violation for different lengths of interconnect lines. The results show the impact of defective grounded shields. 1. Introduction Many techniques have been developed in recent years in order to reduce inductive parasitic effects in high speed in- terconnects [8] [2] [14] [13]. Low frequency circuits could be modeled like resistive and capacitive devices, and the connection between two of them should be considered as a singlenode. This approach is no longer applicable in today’s high performance circuits, where a good prediction of the behavior is required. High frequency operation at the limit of VLSI circuits cause interconnects to have greater impact on the overall system behavior. Consequently, circuit mod- els must include wiring resistance, wiring capacitance and wiring inductance [19]. Signal integrity is an important factor when determining the reliability and performance of electronic circuits, and many resources are therefore required to obtain specific sig- nal integrity levels [11][18]. Signal current variations in a transmission line generate a variable magnetic field. This flux creates induced voltage noise in nearby loops. Shield- ing techniques have been developed to reduce the mutual inductance of signal lines. This allows induced noise to be decreased [14]. The connections of shielding lines to ground could present resistive open defects [13]. A resistive open appears when the conductive material is not completely broken. Via-contacts are a likely place for opens to occur [17] [9] [20] [3] [15]. Random particle induced-contact de- fects are the main test target in production testing [3]. In copper-based technologies more defective connections are expected. The number of open defects is greater in copper than in aluminum [1]. These defects indirectly affect the in- tegrity of signal traveling in adjacent signal lines. Ringing values of the signal may vary significantly. Hence, a faulty behavior of the system can occur. In this paper, we study the effect of resistive open defects in the grounded shielding line connection. We compare the dominant pole loci of the lumped RLC circuit with dis- tributed RLC circuits in order to determine the region of signal integrity violation. Graphs of overshoot and under- shoot values are shown for different interconnect lengths and resistive open defect values. The rest of the paper is organized as follows: In section II simple equations from a lumped RLC circuit are obtained in order to achieve overshoot and undershoot expressions, and a comparison of the root loci for one, two, and three lumped stages is made. Shielding strategies for reducing induced voltage noise are discussed in section III. Section IV shows some aspects of signal quality, and ringing and undershoot values are studied for different lengths of inter- connects for open shield defects. Regions for acceptable or non-acceptable signal integrity level are established in section V. Finally, conclusions are given in section VI. 2. Simple models of the interconnect Proper modeling of parasitic interconnect components is required to evaluate the performance of high speed circuits. In [10] the authors model conductors using surface-only triangular meshes. Interactions between Rao-Wilton- Proceedings of the Eighth IEEE European Test Workshop (ETW’03) 1530-1877/03 $17.00 © 2003 IEEE