522 IEEE TRANSACTIONS ONDEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005 Circuit-Level Reliability Requirements for Cu Metallization Syed M. Alam, Member, IEEE, Chee Lip Gan, Member, IEEE, Frank L. Wei, Carl V. Thompson, Senior Member, IEEE, and Donald E. Troxel, Life Senior Member, IEEE Abstract—Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrate significant differences because of differences in interconnect architectural schemes. The low critical stress for void nucleation at the Cu and interlevel diffusion-barrier interface leads to varying failure char- acteristics depending on the via position and configuration in a line. Unlike Al technology, a ( jL) product-filtering algorithm with a classification of separate via-above and via-below treat- ments is required for Cu interconnect trees. A methodology and tool for circuit-level interconnect-reliability analyses has been de- veloped. Using data from the literature, the layout-specific circuit- level reliability for Al and dual-damascene Cu metallizations have been compared for various circuits and circuit elements. Significantly improved test-level reliability in Cu is required to achieve equivalent circuit-level reliability. Moreover, the required improvement will increase as low-k/low-modulus dielectrics are introduced, and as liner thicknesses are reduced. Index Terms—Aluminum interconnects, barrierless via, circuit- level reliability simulation, copper interconnects, electromigra- tion, integrated-circuit (IC) reliability, reliability estimation. I. I NTRODUCTION T HE International Technology Roadmap for Semicon- ductors (ITRS) projects that an exponentially increasing number of interconnect segments will be required to carry increasing current densities in the years to come. Both trends separately require rapid improvements in interconnect reliabil- ity. Copper (Cu) has been replacing aluminum (Al) as the metal of choice for interconnects due to its lower resistivity and higher resistance to electromigration. While the electromigration- reliability phenomenon in Al interconnects is well studied [1]–[3], the reliability of Cu technology is still under active investigation. In this paper, we contrast the failure mechanisms in Cu and Al technologies and compare electromigration- Manuscript received October 24, 2004; revised May 22, 2005. This work was supported by the Microelectronics Advanced Research Corporation (MARCO) Interconnect Focus Research Center Program, by Semiconductor Research Corporation (SRC), and by the Massachusetts Institute of Technology (MIT)–Singapore Alliance. S. M. Alam was with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139-4307 USA. He is now with Freescale Semiconductor, Inc., Austin, TX 78735-8598 USA (e-mail: salam@alum.mit.edu). C. L. Gan is with the School of Materials Engineering, Nanyang Technolog- ical University, Singapore 639798 (e-mail: clgan@ntu.edu.sg). F. L. Wei and C. V. Thompson are with the Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139-4307 USA (e-mail: fwei@mit.edu; cthomp@mit.edu). D. E. Troxel is with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139-4307 USA (e-mail: troxel@mit.edu). Digital Object Identifier 10.1109/TDMR.2005.853507 reliability assessments at the circuit level. Circuit-level as- sessments carried out at the design and layout stages allow accurate reliability projections, and also allow technology and layout changes for improved reliability with still-optimized performance. We have developed and exercised a tool, SysRel, for circuit-level interconnect-reliability assessments with either Al or Cu metallization, and used it to assess the reliability impact and requirements for Cu metallization. Sections II and III gives an overview of the interconnect metallization schemes for Al and Cu technologies, and out- lines the distinct electromigration characteristics in Cu, in light of the differences in metallization schemes. Section IV describes the atomic-diffusivity models and parameter values used in our work. A default model to compute lifetimes due to electromigration failures is then presented in Section V. Using the diffusivity and default models, we have investigated lifetime trends in a straight-line interconnect that is outlined in Section VI. We have used parameter values from selected pub- lications, as well as those from our own work. Parameter values derived from experiments depend on fabrication processes, ma- terials, and structural details. However, the models and method- ologies we have developed for circuit-level reliability analyses are general, and can be used with any set of experimentally derived input parameters. Simple straight-line interconnects are often studied for ana- lytical and experimental purposes, even though multisegment trees interconnected in a complex fashion exist in actual circuit layouts. In Section VII, we present a set of methodologies for circuit-level reliability analysis with either Cu or Al met- allization in the layout. The methodologies are implemented in a computer-aided-design (CAD) tool, SysRel, with which we have compared circuit-level reliabilities for various circuit layouts. Results are presented in Sections VIII and IX. Finally, Section X addresses the impact of nonblocking vias, a unique phenomenon in Cu technology, on electromigration and circuit- level reliability. II. I NTERCONNECT PROCESSING TECHNOLOGY The fabrication processes are drastically different for Cu and Al due to their differences in chemical properties. Al reacts with SiO 2 to form alumina, which eliminates Al atomic diffusion into the dielectric. Al metallization is processed by subtractive etching in which the patterned lines are formed by etching the deposited blanket Al film. The Al architecture has thick refractory metal layers (made of TiN, Al 3 Ti, or both), at the top and bottom of the lines serving as antireflection coatings and 1530-4388/$20.00 © 2005 IEEE