1414 IEEE TRANSACTIONS ON MAGNETICS, VOL. 44, NO. 6, JUNE 2008 Modeling and Simulation of a Large Integrated Circuit Package Erion Gjonaj , Marcelo B. Perotoni , and Thomas Weiland TU Darmstadt, TEMF, 64283 Darmstadt, Germany CST GmbH, 64288 Darmstadt, Germany The first full-wave signal integrity analysis of a complete computer chip package is presented. The simulations are based on the Finite Integration Technique in the time domain. The handling of the highly complex package geometry and of the huge amount of unknowns arising in the discretization is made possible by use of massive parallelization. The latter employs an optimally balanced partitioning technique. Simulation results including signal delay times and cross-talk couplings are given. Index Terms—Finite-integration technique, full-wave simulation, integrated circuits, parallel computing, signal integrity. I. INTRODUCTION T HE digital circuit industry has traditionally employed numerical tools based on the low frequency approxima- tion with lumped elements. With the ever increasing speed and packaging density, however, high frequency effects within the circuitry become important. Typical electromagnetic compat- ibility concerns at high frequencies include radiation losses, larger delay times and cross-talk coupling [1]. Extensive work has been done to account for these effects in the numerical simulation of integrated circuit (IC) packages. In the macromodeling approach (cf. [2]), for example, first the high frequency characteristics (S-parameters) of interconnect subnetworks are extracted by full-wave simulations and then, a reduced order model for the full device is constructed. The validity of reduced models is, however, difficult to be verified over the whole range of device parameters. Additionally, most of the approaches presented in the literature can be applied only to simplified and/or to a small part of the device. In particular, at the end phase of the design process, there is an absolute need for full-size-full-wave simulations without any geometrical or physical simplification. Because of the geomet- rical complexity of IC packages with thousands of through-hole vias and signal traces mounted on several layers, it is a wide- spread belief among researchers that simulations of this type are impossible. Recent algorithmic progress, however, makes this approach possible, and fully reliable. The key concept is the massive parallelization of field solvers. The use of distributed computing provides sufficient computational resources for the simulation of complete IC packages in fully 3-D geometry. Fur- thermore, this task can be accomplished within short to mod- erate simulation times. In this work, a simulation procedure for the full-wave signal integrity analysis and the results obtained for a very complex computer chip spreader are presented. The work is organized as follows: In Section II, the package considered in the simulations is presented. In Section III, the discretization technique used, the Finite Integration Technique is briefly described. In Section VI, Digital Object Identifier 10.1109/TMAG.2007.916008 Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Fig. 1. Schematic view of the eight metallization layers and the total dimen- sions of the IC package. an optimally balanced parallel partitioning technique is intro- duced and the performance of the algorithm is investigated. Fi- nally, in Section V, the simulation results, including signal delay times, wave forms and S-parameters are given. II. IC PACKAGE The package considered in the following is a multilayer com- puter chip spreader. It connects the semiconductor die with its larger support which in turn is soldered into the printed circuit board (PCB). A schematic view of the stack-up is shown in Fig. 1. The structure contains 8 metallization layers embedded into a dielectric substrate. The metallization is copper and the dielectrics used for the substrate are ABF-GX13 and BT-679FG . Most of the signal traces propagate on the layer FC3. The signal is connected on the top layer to these traces by vias and then routed almost directly to the solder points on the PCB side of the device. The geometry of the package was provided to the authors by the IBM Thomas J. Watson Research Center [3] in form of a Cadence Allegro design layout [4]. The data consisted of more than 40 000 2-D-polygonal elements (pins, vias, traces, solder pads, etc.). The CAD model of the fully 3-D geometry was ex- tracted from these data using the CST STUDIO SUITE soft- ware [5]. This step turned out to be the most challenging in the simulation procedure. Besides the huge size of the data to be processed, the main difficulty in extracting the geometry results from the errors contained in the input data. Typically, Allegro 0018-9464/$25.00 © 2008 IEEE