This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. TITB-00200-2007 1 Abstract— Application-specific integrated circuits (ASICs) have been traditionally used to support the high computational and data rate requirements in medical ultrasound systems, particularly in receive beamforming. Utilizing the previously-developed efficient front-end algorithms, we present in this paper a simple programmable computing architecture, consisting of a field-programmable gate array (FPGA) and a digital signal processor (DSP), to support core ultrasound signal processing. It was found that 97.3% and 51.8% of the FPGA and DSP resources are needed, respectively, to support all the front-end and back-end processing for B-mode imaging with 64 channels and 120 scanlines per frame at 30 frames per second. These results indicate that this programmable architecture can meet the requirements of low- and medium-level ultrasound machines while providing a flexible platform for supporting the development and deployment of new algorithms and emerging clinical applications. Index Terms—Ultrasound systems, Biomedical imaging. I. INTRODUCTION O meet the high data rate and demanding computational requirements in ultrasound imaging, application-specific integrated circuits (ASICs) have been typically used in medical ultrasound machines. With the recent technological advances in digital signal processors (DSPs) and multi-core processors, programmable computing architectures have been introduced and are now commonly used to support back-end processing in Manuscript received August 2007; accepted June 4, 2009. F. K. Schneider was with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195-5061 USA. He is now with the Department of Electronics and the Grad School of Electrical Engineering and Applied Computer Science, Federal University of Technology - Paraná, Brazil (e-mail: fabioks@utfpr.edu.br). A. Agarwal was with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195-5061 USA. He is now at Philips Healthcare, Bothell, WA 98021 (e-mail: anup.agarwal@philips.com). Y. Yoo was with the Department of Bioengineering, University of Washington, Seattle, WA 98195-5061 USA. He is now with the Department of Electronic Engineering and the Interdisciplinary Program of Integrated Biotechnology, Sogang University, Seoul, Korea (email: ymyoo@sogang.ac.kr). T. Fukuoka was with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195-5061 USA. He is now with Hitachi Ltd., Tokyo, Japan (e-mail: tetuya-f@super-r.net). Y. Kim is with the Department of Bioengineering, University of Washington, Seattle, WA 98195-5061 USA (e-mail: ykim@u.washington.edu). commercial ultrasound systems [1-3]. However, ASICs are still used in many ultrasound systems to support more challenging front-end processing. Several approaches were proposed and evaluated for supporting front-end processing with programmable off-the-shelf devices [3-6]. For example, Hazard and Lockwood [3] proposed a fully-programmable architecture for ultrasound machines by utilizing a network of programmable processors. However, their architecture required 132 DSP chips, making it impractical for commercial systems. On the other hand, Pelissier [4] utilized high-end field programmable gate arrays (FPGAs) for front-end processing in a PC-based architecture. While these FPGAs can deliver high computational performance, they are currently 5 to 10 times more expensive than high-end DSPs. Tomov’s proposal [6] on a beamformer architecture based on sparse sampling (i.e., 512 points) and 1-bit oversampled A/D converters utilizes only one low-cost FPGA. However, developing sigma-delta modulators that can provide the required sensitivity (in terms of signal-to-quantization noise ratio) for supporting various medical ultrasound imaging modes remains challenging [7]. As an alternative to Tomov’s work, the goal of our research has been to develop a cost-efficient fully-programmable architecture based on conventional multi-bit A/D converters. We have previously developed new front-end algorithms, e.g., multi-stage uniform coefficient (MSUC) filter [8] and two-stage demodulation (TSD) [7], to reduce the computational and data rate requirements. In this paper, we present a hybrid cost-efficient programmable computing architecture for ultrasound machines. II. METHODS AND MATERIALS In this section, we present the computational and data rate requirements of a typical medical ultrasound imaging system. In addition, a simple programmable architecture that can support both front-end and back-end processing is presented. A. Computational and Data Rate Requirements in an Ultrasound System Figure 1 shows the functional block diagram of a modern ultrasound imaging system based on the commonly-used phase rotation beamformer (PRBF). The received ultrasound echoes Fully-Programmable Computing Architecture for Medical Ultrasound Machines Fabio Kurt Schneider, Member, IEEE, Anup Agarwal, Member, IEEE, Yang Mo Yoo, Member, IEEE, Tetsuya Fukuoka, and Yongmin Kim, Fellow, IEEE. T Copyright © 2009 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending a request to pubs-permissions@ieee.org. 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