This article is protected by German copyright law. You may copy and distribute this article for your personal use only. Other use is only allowed with written permission by the copyright holder. it 3/2007 Schwerpunktthema ◮◮◮ CRC – Concepts and Evaluation of Processor-Like Reconfigurable Architectures CRC – Konzepte und Bewertung prozessorartig rekonfigurierbarer Architekturen Tobias Oppold, Thomas Schweizer, Julio Oliveira Filho, Sven Eisenhardt, Wolfgang Rosenstiel, University of Tübingen Summary The CRC project focuses on the utilization of fast reconfiguration to optimize area, performance, and power. The results are quantified by a synthesizable architecture model and by a commercial architecture. In order to assure good applicability of the research, a C-compiler is co-developed with the architecture. This article provides an overview of the optimization techniques and a summary of current eval- uation results. ◮◮◮ Zusammenfassung Das CRC-Pro- jekt beschäftigt sich mit der Nutzbarmachung schneller Re- konfiguration, um Flächenbedarf, Ausführungsgeschwindigkeit und Verlustleistung zu optimieren. Die Ergebnisse werden anhand eines synthetisierbaren Architekturmodells und ei- ner kommerziellen Architektur beurteilt. Um die entwickel- ten Konzepte auch praktisch einsetzen zu k¨ onnen, wird ein C-Compiler gemeinsam mit der Architektur entwickelt. Die- ser Beitrag liefert einen ¨ Uberblick ¨ uber die Optimierungs- techniken und eine Zusammenfassung aktueller Bewertungs- ergebnisse. KEYWORDS C.1 [Computer Systems Organization: Processor Architectures], C.3 [Computer Systems Organization: Special- Purpose and Application-Based Systems], dynamic hardware reconfiguration, coarse grained reconfigurable ar- chitectures, high-level compiler, voltage reconfiguration 1 Introduction Reconfigurable systems provide the ability to reuse architectural re- sources over time. Typically, for stat- ically reconfigurable architectures, this reuse happens rarely. For ex- ample, FPGAs are often used for prototyping purposes so that the reconfigurable fabric is reused in the range of minutes or even much longer. Reconfiguring such archi- tectures at runtime of the sys- tem is mostly done in academic work trying to reuse the archi- tecture, e. g., for various tasks of an embedded system. Due to the long reconfiguration times imposed by transferring the configuration data from outside the reconfigurable fabric, finding a good partitioning is highly application specific and hardly supported by commercial tools. Newly developed architectures can be reconfigured within one clock cycle, allowing components of a device to be reused within a single application. We call such architectures processor-like reconfig- urable architectures. They usually have a coarser granularity and re- quire less configuration data than traditional FPGAs so that multiple configuration contexts can be stored inside the reconfigurable array and reconfiguration keeps pace with ex- ecution. This yields an additional degree of freedom, which we ex- plore in a design environment that takes advantage of reconfiguration to optimize area, performance, and power. The optimizations pertain to architectural features and compiler techniques since the benefits of re- configurability can only be exploited if applications can be mapped effi- ciently. In the CRC project, we de- veloped a modifiable architecture model (Configurable Reconfig- urable Core, CRC) that can be adapted to the requirements of the compiler. Synthesizing instances of the CRC model enables a de- it – Information Technology 49 (2007) 3/ DOI 10.1524/itit.2007.49.3.157  Oldenbourg Wissenschaftsverlag 157