Parametric Model Checking with VerICS ⋆ (Tool Paper) Micha l Knapik 1 , Artur Niewiadomski 2 , Wojciech Penczek 1,2 , Agata P´o lrola 3 , Maciej Szreter 1 , and Andrzej Zbrzezny 4 1 Institute of Computer Science, PAS, Ordona 21, 01-237 Warszawa, Poland {Michal.Knapik,penczek,mszreter}@ipipan.waw.pl 2 Siedlce University, ICS, 3 Maja 54, 08-110 Siedlce, Poland artur@ii.uph.edu.pl 3 University of  L´ od´ z, FMCS, Banacha 22, 90-238  L´ od´ z, Poland polrola@math.uni.lodz.pl 4 Jan D lugosz University, IMCS, Armii Krajowej 13/15, 42-200 Cz¸ estochowa, Poland a.zbrzezny@ajd.czest.pl Abstract. The paper presents the verification system VerICS, extended with the three new modules aimed at parametric verification of Elemen- tary Net Systems, Distributed Time Petri Nets, and a subset of UML. All the modules exploit Bounded Model Checking for verifying paramet- ric reachability and the properties specified in the logic PRTECTL – the parametric extension of the existential fragment of CTL. 1 Introduction VerICS is a model checker for high-level languages as well as real-time and multi- agent systems. Depending on the type of a considered system, the verifier enables to test various classes of properties - from reachability of a state satisfying cer- tain conditions to more complicated features expressed with formulas of (timed) temporal, epistemic, or deontic logics. The implemented model checking meth- ods include SAT-based ones as well as these based on generating abstract models for systems. The architecture of VerICS is depicted in Fig. 1. At its right-hand side there are visualized the model checking methods offered for real-time systems: bounded model checking (BMC) for proving reachability in Time Petri Nets (TPN) and in Timed Automata (TA) (including TADD - TA with Discrete Data) as well as for testing TECTL (Timed Existential CTL) formulas for TA, unbounded model checking (UMC) for proving CTL properties for slightly restricted TA, and splitting for testing reachability for TA. The modules implementing the above methods are described in [8, 17] and [18]. In the boxes with rounded corners the input formalisms are depicted: both the low-level (TPN, TA) and high-level lan- guages (Java, Promela, UML, Estelle). The languages for expressing properties ⋆ Partly supported by the Polish Ministry of Science and Higher Education under the grants No. N N206 258035 and N N516 370436.