A Multi-channel Symbol Timing Recovery Architecture for 10GBASE-T System Ying-Ren Chien 1 , Jan-Hwa Lee 2 , Hen-Wai Tsao 3 , and Wei-Lung Mao 4 Graduate Institute of Communication Engineering and Department of Electrical Engineering, National Taiwan University 1,2,3 Taipei, 106, Taiwan, R.O.C. Department of Electronic Engineering, National Formosa University 4 , Yunlin County 63201, Taiwan, R.O.C. d92942008@ntu.edu.tw, ewaitlee@hotmail.com, tsaohw@cc.ee.ntu.edu.tw, wlmao@nfu.edu.tw Abstract  A traditional symbol timing recovery architecture that used in 100BASE-T and 1000BASE-T is multi-phase selection based phase-locked loop (MPS-PLL). In 10GBASE-T system, the echo (ECHO) interference suppression requirement is much higher and hence the ECHO canceller is more sensitive to the timing jitter as well than that of 1000BASE-T system. Hence, the MPS-PLL architecture is difficult to implement in 10GBASE-T system. In this paper, we propose a hybrid symbol timing recovery (STR) architecture, which comprises a phase-locked loop (PLL) block accompanies three delay-locked loop (DLL) blocks as a four-channel STR system, and the corresponding finite state machine (FSM) control block that are suitable for 10GBASE-T system. Finally, the complete simulation results, which include automatic gain control loop adaption, frequency offset estimation and correction, PLL phase and frequency recovery, DLL phase recovery, timing tracking, decision feedback equalizer training, echo canceller training and near end crosstalk canceller training in the training mode, show that the proposed four-channel STR architecture is practical. Keywords  10GBASE-T, Frequency offset estimation, Symbol timing recovery (STR), Phase lock loop (PLL), Delay lock loop (DLL). 1. Introduction of Timing Issues For the demands of economical high speed data transmission over shorter transmission distance, IEEE 802.3an work group specifies the next generation 10Gbps ethernet network and termed 10GBASE-T [3].The full duplex transmission over four-pair copper suffers from many impairments, such as inter-symbol-interference (ISI), insertion loss (IL), echo (ECHO), near-end crosstalk (NEXT), far-end crosstalk (FEXT), and alien crosstalk. Besides, a multi-channel timing recovery problem was also pointed out in [1] and [2]. Three different approaches for the four-channel sampling problem were discussed in [1]. The intuitive and direct approach is to adopt independent phase-locked loop (PLL) per channel to adjust the timing on each channel. Although it is theoretically possible, it has some implementation challenges, such as the implementation of multiple voltage controlled oscillators (VCO) on same die may cause the interaction among VCOs. The second approach is to use a single VCO with a phase selector, i.e. a multi-phase selection based phase-locked loop (MPS-PLL). This approach is also used in 100BASE-T and 1000BASE-T system. However, because the ECHO interference suppression requirement, 50dB to 60dB [1], is much higher than that of 1000BASE-T system, and hence the ECHO canceller is more sensitive to the timing jitter than that of in 1000BASE-T. The resulting challenge is that the required number of phases of MPS-PLL is much higher than that of in 1000BASE-T. The third approach is to move the timing recovery after the feed forward equalizer (FFE) and use a digital interpolator instead of analog VCO or phase selector. However, this approach needs zero excess bandwidth channel to permit digital timing recovery after equalizer. In this paper, we proposed another approach for multi-channel symbol timing recovery (STR) problem, which is compatible with the loop timing technique [2]. The paper is organized as follows: In section 2, the proposed hybrid STR architecture is described. The detailed design of PLL- and DLL-based STR architectures are discussed in section 3 and 4, respectively. In section 5, the simulation results demonstrate the functionality of the proposed architecture. Finally, in section 6, we summarize the entire paper. 2. Hybrid Symbol Timing Recovery Architecture As shown in Fig. 1, the proposed system architecture is a hybrid timing recovery architecture, and there are two different clock rates in the system, one is 1.6 GHz, denotes as T/2-spaced, and the other is 800 MHz, denotes as T-spaced, where T is the symbol time. For simplicity, as shown in Fig. 2, we set pair-one with the analog PLL to synchronize the local This work was supported by the National Science Council under grant number NSC94-2220-E-002-021 ISBN 978-89-5519-131-8 93560 - 668 - Feb. 12-14, 2007 ICACT2007