Molecular beam epitaxy growth of bulk GaNAsSb on Ge/graded-SiGe/Si substrate Tien Khee Ng a,Ã , Soon Fatt Yoon a,b , Kian Hua Tan a , Kah Pin Chen a,b , Hendrix Tanoto a , Kim Luong Lew a , Satrio Wicaksono a , Wan Khai Loke a , Carl Dohrman c , Eugene A. Fitzgerald c,d a School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798, Singapore b Singapore-MIT Alliance, N3.2-01-36, 65 Nanyang Drive, Singapore 637460, Singapore c Department of Materials Science and Engineering, Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, Massachusetts 02139, USA d Singapore-MIT Alliance, Room 8-407, 77 Massachusetts Avenue, Cambridge, Massachusetts 02139, USA article info Available online 5 November 2008 Keywords: A1. Atomic force microscopy A1. Reflection high energy electron diffraction A3. Molecular beam epitaxy B1. Antimonides B1. Nitrides abstract We present here the preliminary growth and characterization results on the integration of GaAs/GaNAsSb/GaAs III-V layer structure on Ge/graded-SiGe/Si substrate or simply silicon virtual substrate (SVS). It was found in cross-section transmission electron microscopy (TEM) study that a sub- optimal Ge surface annealing (below 600 1C) was detrimental to the subsequent growth of III-V layer, and surface pitting was observed on the GaAs surface as a result. This surface pit was found to originate from the heterovalent interface between the Ge substrate surface and the GaAs epitaxy. By properly treating the Ge surface with in-situ annealing at 640 1C and low temperature GaAs seeding before epitaxy growth, the above III-V layer structure can be successfully grown with smooth surface morphology. The atomic force microcopy (AFM) results correlated well with the RHEED observation and provided further insight into the quality of three GaAs/GaNAsSb/GaAs samples. The root-mean-square (rms) surface roughness of the GaAs/GaNAsSb/GaAs layer structures with GaAs grown at 650, 610, and 580 1C were 25.9, 6.2, and 1.7nm, respectively. In addition, upon annealing at 750 1C for 1min in N 2 ambient, one of the GaAs/GaNAsSb/GaAs sample showed a 5 K photoluminescence (PL) spectrum that was dominated by a peak with emission energy at 980 nm or equivalent to 1.27 eV. & 2008 Elsevier B.V. All rights reserved. 1. Introduction Compound semiconductor epitaxially integrated with Si sub- strate has attracted considerable attention in the scientific community because of the promising prospect in: (a) mass producing concentrator photovoltaic chip on silicon substrates and (b) integrating high-performance compound semiconductor devices with high-density silicon integrated circuits. Our motiva- tion in this study lies in the significance of using silicon-based substrate for producing III–V compound semiconductor devices, due to the excellent electrical and mechanical properties associated with Si substrate, lower cost due to its manufacturing scalability and vast Si feedstock availability. A vision towards manufacturing III–V devices on 12 in diameter substrate is indeed very attractive. This heterogeneous integration of III–V compound semiconductors with Si, therefore, motivated the persistent pursue of a new class of dissimilar-material substrate or virtual substrate over the past decades [1]. The idea was to engineer the lattice constant and strain of an intermediate layer to match that of the commonly used III–V compound semiconductor, such as GaAs and InP, while employing strain-relieve and defect-confine- ment strategies to produce such novel substrate. By composition- ally grading the Si 1x Ge x interlayer, a Ge/graded-Si 1x Ge x /Si hetero-substrate having offcut Ge terminating surface will result in a small lattice mismatch of 0.1% compared to GaAs [2]. Despite the excellent development, there are challenges in integrating compound semiconductor on Ge-terminated sub- strate. The second motivation for this work is, hence, to provide further insight into the critical MBE pre-growth steps that will ensure the absence of the non-favorable atomic stacking fault formation originated from the anti-phase domain (APD) at the III–V/Ge interface. Although a low temperature seeding process was found to be essential in preventing APD formation [3], this study found that another step prior to the seeding process was also playing a significant role in preventing APD formation. It was found that there exists a sub-optimal temperature regime for in-situ Ge annealing that will promote APD-related stacking fault formation, and, therefore, requires further investigation. The third motivation in this investigation lays in the tre- mendous potential and recent interest in the use of small ARTICLE IN PRESS Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/jcrysgro Journal of Crystal Growth 0022-0248/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.jcrysgro.2008.09.207 Ã Corresponding author. Tel.: +6590219049; fax: +6567933318. E-mail address: engtk@ntu.edu.sg (T.K. Ng). Journal of Crystal Growth 311 (2009) 1754–1757